PXI-6551 DDC Strobe Input on CB-2162 Accessory

[RonC]

Hi,

I am using the CB-2162 prototying terminal accessory to provide signal termination to a PXI-6551, for signal acquisition, using a 2Mhz sample rate (I can drop to 1MHz if necessary). The sample clock is being routed to the DDC/STROBE input on the CB-2162.

The data generating device is standard 10K ECL, so I have configured the terminations and voltage detection threshold according to the NI app note on this subject. DATA in signals are excellent, with high levels of -0.8 V and low levels of -1.8 V. However, the clock signal levels are -0.62 V high and -1.14 V typical, when connected to the CB-2182. When disconnected, the clock signal levels match the data levels. The result is that it is difficult to specify a voltage detection threshold (half the range between high and low) that will work reliably for both data and clock. I have been using -0.95 +/- 0.5 V for testing, but results are not reliable.

The documentation for the CB-2162 indicates the STROBE termination is different than the data lines, but does not say exactly how. There is a series termination indicated, which is fitted with a 0 Ohm resistor from the factory. By experimenting with the value of this resistor, I can bring the clock levels closer to the data levels. For example, using a 330 Ohm resistor bring the levels very close to the data levels.

But, if I use anything other than the zero Ohm resistor (I went as low as 37 Ohms) the HSDIO driver complains the clock is out of spec. According to the specs for the PXI6551, the STROBE and data lines have the same spec ( -2 to +5V). The signal quality looks excellent, and the timing is perfect with respect to the CLK and DATA signals.

I don't understand:

1) How the signal termination is different for the STROBE and DATA lines on the CB-2162

2) Why the HSDIO driver rejects the clock signal when it appears to be a very good signal.

Can anyone shed some light on this?

Thanks,

RonC

[dbell0971]

Hi RonC,

I assume that you are talking about this note below:

http://www.ni.com/white-paper/3525/en

Also, are you referring to this paragraph in the manual:

"The series termination socket for the STROBE/PFI_5 channel is intended for use when the originating source of the signal being applied to the STROBE/PFI_5 terminal of the DDC connector is near the 1 × 2 STROBE/PFI_5 control channel pin and has a source impedance of less than 50 Ω. In this case, you might want to add series resistance to raise the total source impedance to 50 Ω to minimize reflections. This socket is populated with a 0 Ω resistor before the NI CB-2162 is shipped."

If you leave the zero Ohm resistor alone, does HSDIO throw an error?  Can you post a screenshot of the HSDIO error?  How have you terminated the DATA lines?

Thanks,

David B

National Instruments

Applications Engineer

[RonC]

Hi David,

Thank you very much for responding to my question.  Yes to both, that is the note, and also the paragraph I was referring to. I learned a little more today, and now I understand exactly what the series zero ohm resistor is doing. It is, of course, exactly as the manual says, a series termination instead of a parallel termination. Until I understood this, I was experimenting with different resitance values, which appeared to my eye to priduce a 'better' clock signal, but this was rejected by HSDIO.

The termination, presently, for all lines is exactly as shown in the whte paper. A series 50 ohm resistor and a 220 ohm resistor to ground. The PXI-6551 is configured for 50 KOhm input impendance.

My confusion, and my problem, is that the STROBE appears to be terminated internally on PXI-6551 differently than the data lines. The result is that the sensed voltages are different, and I can only provide one set of voltages (detection threshold in the white paper) for both STROBE and data lines. My signal source is a digital recorder (high speed tape recorder DIR-1000L), which uses ECL 10K, 7 Ohm source impedance, voltage levels: High -0.8V Low -1.8V.

All source signals, CLK and DATA, appear to be sourced the same. If, for example, I supply a data line to the DDC STROBE/PFI_5 input on the SCB-2162, the result in the same as when I supply the DIR-1000 CLK signal. That is; high = -0.62V; low = -1.02V. It appears that the input impedance on the STROBE input is not 50KOhms.

No, I do not get the error when using the supplied zero ohm resistor in the F1 jumper location.  I got the error when I was experimenting and now I understand I was putting additional resistance in series with the 50 Ohms that I had there already. I cannot get a screen shot right now, the system is at a customer site, but the error reported is HSDIO Error - 1074116171 Hardware Clock Error. "...make sure it is conencted and within specs..." TO me it looks like a very good clock signal, e.g. if I use 330 Ohm R in the zero Ohm jumper spot, the clock levels are very close to the dat levels, the clock appears clean ansd stable on a 'scope.

So, two points of confusion...

1) Why are the STROBE levels different than the data levels, with the same source signal.

2) What is the error complaining about specifically.

My problem is the one detection threshold I am able to suppky for both clock and data (e.g -0.89 V) provides almost no noise margin, and hence I am getting poor reliability. Too high, e.g -0.83V, and I get data errors, too low, e.g. -0.96V and I get false clocks (down in the grass of the CLK low level)

Thanks,

RonC

[dbell0971]

Hi RonC,

Before getting to your questions, I want to discuss a confirm some of what you've said for anyone else who may read this thread.  First, I was concerned about using a negative voltage for the Clock Source.  However, after reading the article linked below, I discovered this at the bottom of the page:

http://zone.ni.com/reference/en-XX/help/370520K-01/hsdio/hclock_sources/

"The STROBE signal must be a free-running square wave clock. STROBE is sampled at the same voltage thresholds as the dynamic acquisition data lines."

From the article, I'm assuming that you are correct in setting a negative voltage level for both STROBE and DATA lines.

Now to your questions:

1) Why are the STROBE levels different than the data levels, with the same source signal?

      There could be several sources of error, but my first guess would be termination.  How do you currently have the STROBE line terminated?  Is it terminated the same as the rest of your DATA lines?  I've not worked enough with ECL to know how to terminate the STROBE line, but I would expect to terminate it similarly to the DATA lines.  What is in the F1 socket?

2) What is the error complaining about specifically?

     There are also many sources for the 1074115970 error.  It's thrown whenever the clock is out of spec; I've seen it thrown because the voltage levels were out of range, the clock was unstable, or even because no clock was connected.  You mentioned that the error isn't thrown when the 0 Ohm jumper is in place, does it throw the error when you replace the 0 Ohm resistor with a 50 Ohm resistor?  Also, you mentioned that you set the 6551 to 50 KOhm input impedance, how did you set the input impedance?  The KnowledgeBase article linked below details how to set both the DATA lines and the STROBE lines input impedance, did you set both the DATA and the STROBE lines?

http://digital.ni.com/public.nsf/allkb/77562C98A187F9C6862577D2006FE3E2?OpenDocument

Thanks,

David B

National Instruments

Applications Engineer

[RonC]

Hi David.

Thank you for taking the time, over the holidays, to provide these additional comments.

RE the Question 1) comments:

Just to confirm, yes I am setting the negative voltage threshold for both the STROBE and DATA inputs, as recommended in the article. I set these independently, but the levels must be set the same, or an error is thrown. This is the crux of the problem -- I must find a compromise threshold that will work for both the clock and data sensing, and this compromise provides almost no noise margin.

The termination, as currently configured by me, is exactly as shown in the article -- 50 Ohm resistor is series, 220 Ohm resistor in parallel to provide a current path. This termination is currently identical for both clock and data, which leads me to believe the signals are being terminated differently inside the PX-6551. The data line termination works correctly, signals are near perfect ECL, high -0.8V low -1.8V.  However if I take that same data signal and apply it to the STROBE input (which has the same external temination as the data line) then the signal levels are pulled towards ground, and the resulting levels are high -0.62V low -1.02V.

The F1 socket contains the supplied zero Ohm resistor. i.e. factory configuration.

RE the Question 2) comments:

As far as I can tell the clock voltage is within the -2.0 Volt range. There may be noise or transient spikes below this which I cannot see. I have experimented with a number of different R values for the F1 socket, including 50 Ohm. With the 50 Ohm value, I have had momentary success with the clock during one test, but this is not reliable at all. Note that the 50 Ohm in the F1 spot is in addition to the 50 Ohm that I am using as part of the termination scheme -- so effectively 100 Ohm in series when I put a 50 Ohm R in the F1 spot.

Here are some representative results, showing the result of changing the F1 R value, on both the STROBE and data levels...

STROBE R      CLK lo      CLK hi      Data lo      Data hi

(F1 socket)

0 Ohm              -1.13         -0.71         -1.8           -0.8

50 Ohm             -1.38         -0.74         -1.8           -0.8

220 Ohm            -1.57         -0.75         -1.8           -0.8

330 Ohm            -1.64         -0.77         -1.8           -0.8

To my eye, except for the level shift, there was no discernable change in the quality of the clock signal. I can see no reason for the clock to be rejected. Perhaps the additional resistance is causing some instability?

The internal impedance is being set independently for both the STROBE and data lines, and being read back for confirmation. When I make the change between 50 Ohm and 50KOhm, I can see a change in the level of the clock signal, so I am pretty sure this is working properly, but I will check again today (the method I am using). When the internal impedance is changed to 50Ohm, the levels are pulled even higher. I can measure those today. I will also check the exact method I am using to set the impedance levels.

Thanks,

RonC

[RonC]

Just a small but important update...

The problem with the clock being rejected was finger trouble on my part. When I was changing resistance values in the F1 jumper location, I continued to measure the voltage at the DDC STROBE header pin. I rang out the circuit, and discovered the voltage being sensed is actually at the other end of the F1 spot, where the "F1" is on the silkscreen. When I measure the voltage at the correct location, I can see that I was pushing the clock voltages out of range of my threshold voltage, and the clock was not being detected. So, the error message was correct (as it almost always is) and of course in hindsight it all makes perfect sense.  :manembarrassed:

I have also made some progress on getting the clock levels closer to matching the data levels. Before, and as a starting point, the termination was exactly as recommended in the app note; which is a 50 Ohm R in series for impedance matching, and 220 Ohm to ground to provide a current path for the ECL driver. This resulted in perfect data signal levels, so it was left alone.

After discovering the above, I removed the 50 Ohm series resistor in the small termination circuit, planning to use the F1 location to experiment with R values. With zero Ohms series resistance, the clock levels were better, but still not close enough to the data levels. Data levels are perfect ECL, low -1.8V, high -0.8V. Clock was low -1.17V, high -0.77V.

Next I changed the parallel 220 Ohm resistor to 1000 Ohm, and the resulting clock level was low -1.31V; high -0.79 V. Clock was fairly noisy, so I added a 7 Ohm resistor in the F1 location, because the documentation for the ECL device I am using indicates a source impedance of 7 Ohm. This cleaned up the noise a little, and slightly improved the voltage levels to low -1.39V; high -0.79V. I have also done some experimenting with a simple noise filter (56 Ohm R to 0.1uF cap) which seems to help, but needs some further experimenting with values.

Regarding the input imedance for the STROBE signal, I checked and I was setting the value as indicated in the post above, i.e. setting niHSDIO property 'SampClk.Impedance' to 50,000. I also read this back to confirm the setting.

In summary, I think I am getting close to a workable solution, but I would still like to know what is different about the input circuitry for the STROBE, compared to the data signals. Knowing this would help a great deal for those wanting to develop proper termination circuits for the STROBE signal. This would be a great help not only to me, but to others who may experience a similar problem in the future.

RonC

[dbell0971]

Hi RonC,

I apologize for the delayed response, I've been away from the office for the past couple of days.  I'm working to get a hold of the schematics for the 6551 to see how the STROBE is terminated.  I'll post back here when I have more information for you.  Have you had any updates in the past couple of days?  I'm glad we figured out the error being thrown at the least, hope all is well.

Sincerely,

David B

Applications Engineer

National Instruments

[RonC]

OK thank you David. If you can locate the schematic that would be a great help in understanding why the STROBE input behaves differently.

No real progress to report; I did some more testing on Monday, and I was still having trouble with false clock triggering on noise. I think I will experiment with setting separate low and high detection thresholds, to introduce some hysteresis. Problem with that is I am further reducing the noise margin. I may also change the 1000 Ohms parallel resistance to ground to 1500 Ohms and see if that gives me a larger range between high and low on the clock. I am a little concerned that this will further reduce the clock signal current and increase the noise sensitivity.

I don't pretend to really understand what I am doing. I have picked up some knowledge of electronics over the years, but I am a mechanical engineer by training. I just know enough to get into trouble.

I will be testing some more tomorrow (Thursday).

RonC

[dbell0971]

Hi RonC,

Please check your private messages, I've sent you some important contact information there.

Thanks,

David B

National Instruments

Applications Engineer

[RonC · Accepted solution]

With help from the National Instruments application engineers, this problem has been solved.

The solution for this was...

When interfacing ECL signals, it is best to use the CLK IN front panel SMB terminal to connect the ECL clock. The STROBE input cannot handle the full ECL voltage range.

Another important piece of information that was not clear (to me at least) from the documentation, is that the clock detection and quality checking is done independently of the data line detection. So, one can set the voltage thresholds for HI and LO detection based on the voltages of the data lines only. It is not necessary to consider the voltages of the clock signal for data detection.

RonC