Hey, I am new to FPGA and am trying to write a VI to output a duty cycle to control a computer fan. The fan opperates at 25kHz. I attached the VI. I was wondering is this the best way to write the code or are they more efficient methods?
I'm using 1600 ticks per cycle and a 40mHz clock for timing. The dutty cycle input is in percentage and scaled so it increments by 0.0625 or 1/16 to get interger tick outputs fro high and low. The indicators are just there for debugging and will be removed before compiling. I guess I should probably do the dutty cycle and frequency to low and high ticks calculation on the host RT and pass just the high and low tick values to the fpga?
Note: I just used LabView to write this and not an FPGA VI because I do not have it installed on this computer. The "wait until next ms" will later be converted into "wait to next tick" and the boolean replaced with an digital output node.
Thanks for any input.
