NI FlexRIO 7962

[Sowmini]

Hello everyone,

I am currently working on a FlexRIO platform (NI FlexRIO7962) and the dual channel DAC board from Active Technologies (AT1212) to develop a multi-channel Arbitrary waveform generator. My application needs to generate waveforms with the following specifications

Bandwidth: 200 MHz

Centre frequency: 300 MHz.

Duration: 1.25 ms.

The sampling rate of AT1212 DAC is 1.25GHz. This high rate is achieved inside the FPGA by the simultaneous read of eight consecutive samples at a rate of 156.25 MHz thereby ensuring the final rate of 1.25 GHz. 

Since, my application needs to store longer waveforms, I need to make use of the on-board DRAM. This creates a limitaion, as the maximum rate at which the data to could be read to the FPGA is 100 MHz. Also, the DRAM being 128 bits wide, I can read a maximum of 8 samples at a time which gives me the maximum rate of 800 MHz. But I need to match this to the final 1.25 GHz. This calls for the need for an interpolator/resampler.

Ideally, I need a fractional interpolation rate of 1.5625.  But my concern is how do I implement such an interpolator? Let us make the interpolation factor a round value to 1.6. The maximum clock that could be generated inside the FPGA would be something less than 400 MHz. So how do I implement an interpolator that converts my 781.25 MHz (1.25GHz/1.6) to 1.25 GHz? I suspect the feasibility of implementing such a block considering the maximum FPGA clock ( which is way less than 700- 800 MHz).

It would be really great if someone could suggest the feasiblilty of implementing such a scheme and get me some inputs. I would really appreciate if you could please share some ideas on this regard.

Thanks a lot,

Sowmini

[Dave.T]

Hello Sowmini, 

The 7962 has two banks of DRAM, each capable of providing 128 MB at 100 MHz, or 1.6 GB/s * 2 = 3.2 GB/s.  

If you read from both banks simultaneously,  you should be able to provide data at a suitable rate to the DACs

Dave

[Sowmini]

Hi Dave,

Thanks a lot for the sugestion. Unfortunately, I have to implement two channels per FlexRIO board (since the DAC board by itself is dual channel). Thus DRAM 0 is dedicated to channel0  and DRAM1 for channel1.

Thanks,

Sowmini