10-11-2012 06:09 PM
Hi,
I'm trying to measure a PWM signal generated by an absolute encoder. The encoder outputs a PWM with a period of approximately 1000 microseconds. This correlates to about 0.4 deg/microsecond.
When I run an FPGA code that has a counter that counts ticks while the PWM is high, the counter takes approximately 265 ticks per loop (and increases when other I/O readings are made) - according to the benchmark timer I've incorporated into the code. This means that the loop requires about 6-7 microseconds to take a reading from the DIO. This correlates to a couple of degrees in resolution which is not a good enough for our application to read from the encoder.
Is there any way to increase the speed of the FPGA? I've included a screenshot of the FPGA code as well as the project containing the test VI.
10-11-2012 06:12 PM
I should clarify that in the picture, the "Period" is the while loop period. The "period (Ticks)" is the amount of time that the PWM is returning a high voltage.
10-16-2012 07:58 PM
Hello NIo33,
Have you benchmark the rate at which the PWM signal is coming in from the NI 9403 module? What type resolution are you trying to achieve? I do not see to many ways to pipeline your FPGA code.
Paul-B