Digital net and De Morgan curiosity

[flanguasco]

While implementing a SN74196 (Presettable Decade Counter) as a hierarchical block I have found a strange behavior that I can't understand.

Looking at the attached circuit you see that the IC inputs, LOAD/COUNT and CLEAR, are connected to an OR gate with two inverted inputs.

I have firstly used an OR gate and two NOT at the inputs but it didn't work: a negative pulse on the CLEAR input correctly set all the Q outputs to zero on the falling edge but the following rising edge set all the Q outputs to the values currently applied to the Data inputs (wrong).

After a few trials I have replaced the OR gate and the two NOTs with the De Morgan equivalent, just a NAND gate, and everything was then working fine.

Now my question is: why this? Where is the difference in the two versions of this circuit?

Is it related to the sequence used by Multisim 13 in evaluating the net events?

Ciao and thanks for the attention.

Franco

[Dennis_Knutson]

For Multisim questions, you should post to the Circuit Design Suite board. This board is for NI digital I/O devices.

[flanguasco]

Yes, you are absolutely right and I realized my mistake just few seconds after pressing the [Post] button.

This happened because, being new on this Forum, when I started from the "Circuit Design Suite" board I was always directed to a Search page with no place for writing my message: from there, clicking around, I finally arrived to a page where I could make my post and I did it, without realizing that I was in the Hardware board.

Ciao, for now, and please please accept my apologies .

Franco