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Using one counter (Dev1/ctr0), how to prevent activation (High state output at Dev1/PFI13) of another counter (Dev1/ctr1)?

Hi, i'm using the PCI-6255 and PCI-6251, both have 2 counters. I have the problem that when i use just one counter, the other generate a high output in the PFI line during the time when the first counter is active. It is possible to avoid this situation? I show the issue in the time diagram.

 

Counters.png

 

Thanks

 

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Hi ivkicin,

 

Could you share with us how are you creating the tasks for the Counter outputs?? It is possible that if they are in the same task the default state for the Counter channel is high.

 

Does this happen with both Boards??

 

Have a great day!!

Juan Arguello Director Support Services @NI
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if this is finite counter generation (not 1 pulse, not continuous samples), it uses both counters, the second being the gate for the main one (running continuously). So, you see this gate on default output.

Workarounds:

1) in other tasks that use counter1 force to use not default output (Channel property node -> counter output -> pulse -> Output terminal). Set it to PFI12 for example, check board Device routes diagram in MAX  - it should have direct route (green box), not through other subsystem

2) Try to set in this task main counter to be counter 1. And modify its output terminal, if your counter 1 default output is wired for some other task.

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