Stacking Output Delays

[negnin]

Hi All,

I'm having some problems implementing a delay for an output signal on FPGA.

Basically I need my code to respond to signals with a delay, but during that delay it should still be able to respond to the next signal with the same delay time. However, right now if the pulse is called with the delay that loop is ignoring the next calls to it.

I've attached a diagram of my signals and desired output to illustrate my problem. I've also included a simplification of my code as vi and png.

I've tried to dynamically change the delay time based on if the pulse loop is active, but that doesn't seem to work (not in attached vi).

I'm now thinking that 'wait' might not be the way to go and that I should implement an array with timestamps. The pulse loop would read the earliest array element and execute the pulse generator when timestamp + delay == current time.

I would appreciate your thoughts on this. Any ways to implement this better?
Thanks a lot in advance!

[Matt_L]

Hi Negnin,

Something along the lines of the timestamp would be a possible solution.  You could add a third loop that acts as a fast tick counter and writes to a local variable (just have to be careful to avoid overflow).  Instead of delaying in the pulse generation, you can read the timer variable when Pulse is true, and store this in an array/memory element so you don't miss anything.  Then, have the pulsing code execute only when the difference between current and recorded time is the delay amount (very similar to what you mentioned, that's just how I thought my way through it).  Once you've found an elapsed time, delete that element from the array so the next timestamp can be considered.  But the key would be using another loop to track time, since we don't have timestamp data types on FPGA.

[negnin]

Hi Matt,

Thanks for the reply.
I've implemented the 'time stamp' solution using arrays. The logic works great (tested on a vi not running on the FPGA), but the FPGA is complaining about 'arrays must be fixed size in current target'. I started a new thread on this problem:

http://forums.ni.com/t5/Counter-Timer/FPGA-dynamically-changing-array-problem/td-p/2869430

Thanks!