Help with PCI-6602 gated counters

[bill_gilbert]

I'm trying to help a researcher get a PCI-6602 working as a four channel gated counter. They want to read and reset the counters at about 350hz, putting the
readings in a buffer to get a continuous stream of readings.

We've used the Counter-Continuous Output.vi to generate a 350 hz pulse output that he wants to use as a gate or sample clock on counter7. Works like a
charm. Wired that across the terminal block to Counter0 gate.

Not so much luck with input examples. I've been trying to get Counter - Count Edges (Continuous Clock).vi to work. Even with valid input channels
configured, it fails with error code -201298 (see dialog shot). I can get it to run by changing the boolean input to the DAQmx property
CI.CountEdges.CountReset.Enable from TRUE to FALSE. Then it at least counts, but just totalizes pulses continuously without resetting. Close, but no
cigar. Haven't  found any combination of input channels etc that will make it run with the boolean set TRUE. Makes me nervous when hardware example code fails right off the bat. 

The 6602 manual describes the action we want in the section on Duplicate Count Prevention, but gives no hint as to how one would achieve this with
DAQmx. Anybody have any useful suggestions? Answer might also help the person who posted "Running 6 counters at the same time"

[John_P1]

Instead of configuring a Count Edges task, configure a period measurement.  Use the external signal that you want to count as the timebase, and use the 350 Hz clock as the terminal for the period measurement.  Measure the result in terms of "ticks".  You'll need to turn on duplicate count prevention if it is possible that you might receive 0 ticks in a given period.

The Duplicate Count Prevention property node is pretty well hidden...

In case you were curious, the reason that your first approach didn't work is that the 6602 uses the same internal terminal for the sample clock as it does for the count reset signal.  Newer STC3-based hardware (e.g. X Series) has a dedicated sample clock line so you can use both at the same time.

Best Regards,

[bill_gilbert]

Thanks John! This solution never would have occurred to me.

After I posted this I realized we could probably use the counters without the hardware reset, and handle that in labview. Just came from the lab and we got it working with 4 counters using interrupt data xfr. Made a reentrant vi to take the array of values from each counter read and subtract n from n+1 using an uninitialized shift register. At higher speeds this will hit the wall at some point though.

We'll try your suggestion ASAP.

BG

[bill_gilbert]

Actually never got around to trying John's solution. We just used a reentrant differencing vi with an unitialized shift register to subtract subsequent readings. Since it is only collecting the readings every few hundred Hz, works fine, CPU not breaking a sweat. 4 channel example vi posted below: