660x weak pull-down resistor schematic

[sam.broyles]

The 660x spec sheet mentions that the Power-on state has a Input (high-Z) with weak pull-downs, but I cannot find a schematic with this weak pull-down resistor value.

I want to measure a clock signal on my DUT without loading or distorting the signal, so I plan to use a buffer. I'm concerned about the required drive current to overcome the built-in pull down resistors and the resulting threshold requirements of my PXI-6608 counter.

If anyone has a link to recommended buffers, level shifters, or a knowledge base article with an example circuit, it would be much appreciated!!

http://www.ni.com/pdf/manuals/372141b.pdf

[johnsold]

From the Input high current specification of 200 uA at 5 V you can get an estimate of 25 kohms (which also happens to be the minumum input impedance listed).

Any CMOS buffer with compatible voltage requirements should work for your buffer as far as loading is concerned.  The other matter is the speed.  The 4000 series CMOS devices are not very fast. Some other logic families are much faster.

Since you are building test equipment, consider how you will protect the inputs of the buffer from electrostatic discharges when changing DUTs.  Many simple input protection methods will either slow down the system or add loading that you were trying to avoid.

If you give complete information about the signal/DUT device, someone may be able to offer more specific recpmmendations.

Lynn

[sam.broyles]

I am attempting to measure a 16.384 MHz clock driven by a Fairchild Semiconductor NC7SV126 buffer to a microcontroller.

http://www.fairchildsemi.com/ds/NC/NC7SV126.pdf

After some research, I like the TI SN74LVC1T45 (420 Mbps max), single bit dual supply transceiver. This offers 2 supply rails, but it does not offer an enable pin. I may have to add a relay to connect VCCB to GND so that the signal from the test fixture to the PXI-6608 is not always on. Connecting the VCC to GND switches the input/output ports to a high impedance state which will not load the DUT circuit and should protect the DUT and buffer from ESD damage.

http://www.ti.com/product/sn74lvc1t45

The DUT supplies a 3.3V rail for the NC7SV126 buffer which could be connected to the VCCA of the SN74LVC1T45, and the 5V rail from the PXI-6608 could be connected to the VCCB of the NC7SV126 buffer.

quick specs:

NC7SV126 at 3.3V VCC = VOH 2.2V min, VOL 0.55V max

SN74LVC1T45 at 3.3V VCCA = VIH 2.0V min, VIL 0.8V max

SN74LVC1T45 at 5.0V VCCB = VOH 3.8V min, VOL 0.55V max

PXI-6608 = VIH 2.0V min, VIL 0.8V max

Also, here's a good application note from TI:

Selecting the Right Level-Translation Solution

http://www.ti.com/lit/an/scea035a/scea035a.pdf

[johnsold]

Afer just a quick glance at the data sheets, it appears that his may be a good choice.

The SN74LVC1T45 can source 32 mA with a 5 V supply.  Perhaps you could use a second device as the VCCB switch for the buffer device.  Faster, cheaper, and easier to control than a relay.

Lynn

[sam.broyles]

I'll use the TI TS5A3153 to switch the VCC2 of SN74LVC1T45 between GND & 3.3V from the DUT. I'll control the IN of TS5A3153 with a DIO pin from the PXI-6608. I'll power the TS5A3153 and the VCC1 of SN74LVC1T45 with the 5V from the PXI-6608. This will isolate the DUT clock and DUT VCC when the measurement is not being performed.

http://www.ti.com/product/ts5a3153

-- Sam Broyles

[sam.broyles]

Here's a snapshot of my level shifting circuit.

6608 connections: BUF_+5 is the +5V rail, BUF_EN_1 is DIO_0, CTR_0 is CTR 0 Source PFI-39, BUF_GND is DGND.

DUT connections: 3V3 is a supply rail from the DUT, GDC_16_384MHz_CLK is the signal to be measured.

-- Sam Broyles

[johnsold]

That seems like it should work.

Lynn

[sam.broyles · Accepted solution]

It worked great. I look forward to adding this to my next ITA PCB.