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cRIO System Configuration Information (CRI) Library

The latest release version of CRI has been posted to the LabVIEW Tools Network VIPM repository. 

 

vipm://ni_lib_cri_lv2010

 

We decided to align the CRI version number with the earliest LabVIEW release it supports, so the current version is 2011.0.3.7.  Please ignore the 'lv2010' in the link above. This is an unfortunate historical artifact.

 

We are working on a release for LabVIEW 2013 which will include support for the latest hardware including the 9068 controller. We hope to post this in the next two weeks.

 

 

 

authored by
Christian L, CLA
Systems Engineering Manager - Automotive and Transportation
NI - Austin, TX


  
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Message 41 of 85
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Hi there!
I am using a cRIO-9076 with NI 9223 and two NI 9472 DSUB modules on it. When I use the "CRI Get Remote cRIO System Info.vi", the digital ports 4 and 5 of the 9472 are always set to high. When debugging, I can see that it happens exactly at the moment where "cri_cRIO-9076 Modules Data.lvbitx" is referenced.

Is there any way to avoid this?

 

Greetings

 

Edit: I just realized that it apparently happens another time after the referencing of the bitfile...

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Message 42 of 85
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hi i am a beginner with compact rio. when i want to configure my compact rio (9024)  the picture of systeme appear broken and i cant registre my configuration 

 

thanks 

meddeb safouene

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Message 43 of 85
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Hello meddeb,

 

This particular forum is specifcially intended for support of the cRIO Information (CRI) reference design, and is not monitored by general support engineers. Please post your question in one of the product forums such as http://forums.ni.com/t5/LabVIEW/bd-p/170 or http://forums.ni.com/t5/Real-Time-Measurement-and/bd-p/280 .

authored by
Christian L, CLA
Systems Engineering Manager - Automotive and Transportation
NI - Austin, TX


  
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Message 44 of 85
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Hi there,

 

I am new to cRIO. I am currently building a application to pass data from a FPGA module to the host computer, then log that data to a file. I don't believe I am using scanning mode (the option was never provided, and i wrote code under the FPGA module).

 

The module I am currently using is the NI 9215. Listed in its documents sheet is a sampling rate of 100kS/s. Looking at the data log this cannot be correct, as I collected around 10 seconds worth of data with less than 2k points of data for each channel (4 channels, ie 4 signals).

 

What are the likely points of error? Moreover can I adjust the actual sampling rate in any way using the labview programming language?

 

 

 

I am also looking for a method to retrive data regarding the cRIO using Labview, things such as model number and function (NI 9215, 2210, etc), Analog, digital, input, output. Is there a pallate for this?

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Message 45 of 85
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The 100kSa/s is divided among all the channels on your card.  In other words, its the aggregate sample rate.  So you should be getting 25kSa/s for every channel.

 

How are you extracting data from the fpga?  If you are writing to a DMA fifo and reading it in the RT code, be aware that you are reading fast enough so that data is not overwritten before it is read from the fifo in the RT loop.

 

The fpga is fast, but the RT code loop may not be able to keep up with the sheer volume of data.

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Message 46 of 85
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I have wired the FPGA channels directly to a VI under the host using a "Open FPGA VI Reference" inside the Host VI. 

 

There is no code under the RT. 

 

I have read about the DMA fifo and understand how it functions, but am still unclear to its purpose. Can you clarify this a little?

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Message 47 of 85
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The fpga loops at 40MHz & provides fresh data at the maximum per channel sample rate of your C series module.

 

However, your RT loop does not go that fast.  So you will get data at the maximum loop update rate in the RT.  You can see this by hooking up to a variable voltage source on a channel and then varying the voltage output.  It does not seem to get all the samples, since the values update rate are limited to the RT loop rate.

 

The way around this is to use a fifo, so that no data is missed.  Its kind of like a Q, but with a fixed size.  If you don't read fast enough in the RT loop, data will be overwritten by the fpga.  In the RT loop read large amounts of  data (multiple samples) in a single read since you can't loop fast enough.

 

Look at the fpga programmers guide on the NI site.  Its very useful.  Also look at dma fifo fpga examples to get started.

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Message 48 of 85
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Thank you for the suggested information to read (dma fifo examples and fpga programmers guide). I am currently reading it.

 

I have a few other questions:

 

Is the RTOS nessicary for simple data stream acquistion? Can the FIFO be implemented on the Client (PC) directly?

 

Under http://www.ni.com/white-paper/4534/en/ in "hostread.vi" there is a item called "fpga period". I fail to understand what FPGA Period is used for. From my understanding the clock rate on the FPGA should not be adjustible, yet on the frontpanel there is something to adjust the setting "FPGA Period (us).

 

 

Again thank you for your insightful response and time.

 

 

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Message 49 of 85
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Yes you will need the RT to read the FIFO, I don't think you can read the fifo directly in the PC; with the latencies of tcp-ip involved, your buffers would probably get overwritten anyway.

 

You can also "time" your sample rate on the fpga by putting a ms timer in the loop and adjusting the value via a front panel control on the fpga VI.  This will allow you to specify whatever (slower) period you want, subject to the max sample rate of your hardware.

 

I don't have the manual or hardware available, but there are certain extension chassis that do not have/need an RT controller.  You talk directly to the fpga on the backplane via shared variables.  In this case you could access the data directly into your PC by reading those shared variables, but I am not sure of the sample rates available when using this method.  It might not be as fast as the DMA fifo method.

 

There is also a method called "scan mode" that makes programming a lot simpler, but obviously, the simpler the method, the less flexible it is, and if you are need sample rates approaching the limits of your modules, then these may not be appropriate for you.

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Message 50 of 85
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