Since you need Master clock for both read/write in the slave mode,better use PFI connected to SCLK.And make this as a
sample clock for the digital IOs and falling/rising edge as a trigger for MISO and MOSI DIOs.
I suggest to use one more digital input to see the clock pulses (by short circuiting PFI to this line)
, as you can not read through the PFI.
We used the reference design to implement a SPI interface (half duplex) with a PCIe 6251 as a master to control a TI DAC and it worked as intended. The only minor problem was that we would have to send the commands to the DAC at least twice before it would register it.
We are trying to use this implementation on a USB 6211 board in our design for the same task of controlling the TI DAC. We are facing a couple of issues with this USB DAQ board: The RegenMode property used in Init CorrDIO.vi is causing an error -200452 and 'Sample Clock' option for DAQmx Timing.vi in Run CorrDIO.vi is also not supported.
We are not worried about the SPI clock in our design and can go as low as 10KHz. We are hoping we can use the SDW library with SPI reference design on USB 6211 any help solving this issue will be greatly appreciated.
Hi Sandarsh -
I'm glad to hear the SDW library worked for you without any modifications! I'm not sure why you have to issue the commands twice. It may be a function of the DAC's write/read timing.
As evidenced by the error code you reported (-200452), it looks like the USB-6211 is not a Correlated DIO device. Its DIO lines can be used in Static operations only, which means the examples in the "Serial Protocol Communication" whitepaper can't be used with it. Earlier in this thread, an example of using Static DIO to create a SPI transaction was linked in a post. I recommend using that as a rubric for implementing SPI on the USB-6211. You may also want to send a message to Priyatham, who's posts in this thread indicate he's working on the same type of application.
Thanks for the advise, but I really cant use SCLK as the external sample clock as its not free running. I have tried to use SCLK as a trigger, but the Pause trigger available in Gen. Engine is level sensitive and not edge sensitive, and I cannot use a pattern match trigger(which has the option of falling/raising edge triggers) in the Generation Engine. Is there any other way to trigger on a edge in a Generation Engine other than using it as a start trigger. Plz. let me know.
I have been trying to use 6551 as a SPI Slave. Here's what I have been doing:I have a Dynamic Generation engine and a Dynamic Acquisition Engine in the SPI Slave State. I'm triggering both the Acquisition and the Generation Engine on the falling edge of the CSN, then Im generating the SPI Slave data on MISO bit by bit using a sample clock that is 6x my SPI Master clock. I need to send out data on 17-24 clocks of my SPI clock after the CSN goes Low. So I had assumed once I use the CSN as my Gen. trigger I can send out data on the 102 - 144 (17x6 - 24x6) clocks of my sample clock. But its not working out that way, What I see is a delay of my data on MISO after the CSN goes low. So I was wondering if there's some sort of software delay in between the Generation trigger and the Generation Data. I dont care if there's a delay which is deterministic and the same every time, but I probably cannot deal with varying delays.I'd greatly appreciate any help on this.
Hi Priyatham -
Is there any other way to trigger on a edge in a Generation Engine other than using it as a start trigger.
Have you tried the Advance trigger? It's documented in the NI Digital Waveform Generator-Analyzer Help.
I have been trying to use 6551 as a SPI Slave...
You may want to create a new thread in the Digital I/O board to get more views/responses on this post.
I have an SPI protocol that is used to communicate from a main CPU to a micro. In my test I am removing the CPU to test the micro. My PC (LabVIEW) will replace the CPU and act as the master to communicate with the micro.
So far I am able to correctly send a command to the micro, but my problem lies in the response. I am supposed to wait for a data ready line to toggle, and then send "stuff data" from the master to clock in the response.
1. Is there a way to set up an interrupt so that LabVIEW will "wait" until my data ready line from the micro goes high? I have attempted to poll, the pin, but the pulse width of the data ready is very short so I am often missing the toggle. I can add HW, but if there is an easier way...
2. When I am able to read back the data from the micro, I am using the SPI library and I am able to see the MISO line on the digital waveform of the front panel. How can I get this data into a byte array so that I can parse the data?
These are the two isses I am currently working on. Any suggestions would be appreciated. I am new to LabVIEW so any obvious solutions may not have come to my mind yet.
I got an answer to this from Raajit Lall, High Speed Digital I/O Product Marketing. Thought would post it here for anyone that might have the same problem:
There is a deterministic hardware delay between the generation trigger and the generation data. This delay is 32 cycles + 160ns and is always the case. It depends on your clocking rate of course, so if you have a 100 MHz clock then it is 320ns + 160ns. If your clock is slow this delay will seem large. To reduce this delay you can speed up your clock and over sample your data. This information is in the specifications document.
Now I've got one more question:
have two states – SPI Master and SPI Slave. In my SPI Master state I configure the registers and write an instruction config done. As soon as my DUT detects this instruction it takes over as the SPI Master and now I have to acquire the signals it sends out as an SPI Slave. But as I have these two configurations in two different states, I think its taking some time for the state transition from SPI Master to SPI Slave - as a result I’m not able to acquire the very first signal my DUT sends out. I’m rather acquiring signals after a period of time. Is there any way to avoid this state transition delay? Is there a better coding practice for this type of situations? Would merging the two states help? Merging these two states might be messy in my case, but I will give it a try if that’s the only option.
Hi Jamie -
1. LabVIEW is just the programming language you're using. I'll need to know which hardware device (PCI-6536, PXI-6551, USB-6259, etc.) you're working with to help you out. I'm pretty sure all devices that work with the SDW library's waveforms also have a Start trigger for their generation (Digital Output) tasks. Check the documentation and example programs for your hardware to find out how to configure triggers. (If you're working with an NI-HSDIO based device, consider using the Advance trigger for multi-message interactions.)
2. I left this task up to the developer, because every implementation is necessarily unique. You can study the example I wrote for the HSDIO Hardware Compare (HWC) engine in the code attached to the Serial Protocol Communication whitepaper. It should give you some idea of how to approach the job.