I2S: Encoding and Decoding Signals in LabVIEW

[PrasanthTP]

Dear all,

I need to decode data from Digital MEMS microphone (ICS-43432) using NI myRIO 1900.

I have attached below the screenshot of thte sytem block diagram of microphone.

In my circuit, I am using only one MEMS circuit and I have connected the

• LR to 0 (GND)
• WS to Connector A: Digital Input 0
• SCK to Connector A: Digital Input 1
• SD to Connector A: Digital Input 2

I understand that I can use FPGA in myRIO to establish I2S communication and tranfer the data from FPGA to RT Host using DMA FIFO

I have found your actual post from the link below

https://decibel.ni.com/content/docs/DOC-1230

When i tried to run this program in myRIO, i am neither getting any significant output nor I understand how the program works.

I suspect the program is running too fast when i obseved the iteration counter both in FPGA and in RT.

I am wondering how do i configure the loop speed to that of my preferred sampling rate.

I need to perform sampling, fs at a rate of 48 KHz. 

From the data sheet of the microphone, i realised that 

SCK = 64 x fs = 64 x 48 KHz = 3.072 MHz

It's also mentioned that it produes 24 bit data

Can anyone help me explain or understand how this I2C program shown below works.

If not, can you provide me with some reference links.

Thanks in advance 

FPGA screenshot

Real Time Target Screenshot

[Christian_L]

I'll try to give you some help on this example.

• The Read Loop, which is the blue structure is a Single Cycle Loop and runs at the clock rate of the FPGA, which is 40 MHz by default. 
• The Read Loop synchronizes itself to the I2S signal by looking for the edges on the SClk and WS (LRClk in the FPGA code), so you do not need to configure the loop speed. Based on these edges and the number of bits, the read loop uses a simple state machine (implemented using the various case structures) to read the SD line, collect the data bits in a register, and transfer the collected data using the DMA FIFO.
• After starting the FPGA VI the Read loop sits in the Wait for Start case. After starting the read operation from the Host VI, the Read loop goes into the the Synch Start case.
• In the Synch Start case, the FPGA is reading the WS (LRCLk) line looking for a falling edge, which indicates the start of the Left Channel, and goes into the Read state.
• In the Read state, the FPGA VI looks for rising edges on the SCLk, which is the indicator to read the SD (SData) line. On the next cycle of the read loop it reads the SD line and writes the bit to the Sample Value register.
• The Bit Counter register keeps track of how many bits have been written to the Sampe Value register. After the configured number of bits have been collected, the Sample Value is written to the DMA FIFO.
• While looking at the SClk, the FPGA VI is also looking for the WS (LRClk) signal to change, which indicates the end of the current channel and beginning of the next channel. At this point the Bit Counter is reset and the VI is starting to collect the bits for the other channel.

Looking at the datasheet for your microphone, the sensor outputs 24 bits per channel, but skips the first sample. Therefore you need to set the number of bits per sample to 25. After acquiring 25 bits from the SD line, you will have the 24 bits of valid data in the Sample Value register for transfer to the RT host VI. In the host VI, you should mask the data to the 24 bits to remove the extra bit acquired. This can be easily done using the Boolean And function (see example).