I am trying to implement I2C on a DAQ card. We plan on running the system on Labview 2009. Did any one try this before? What should I do if I want to use these library and vi? Thanks.
Hi Tan -
IDW was designed to work only with Hardware-Compare-enabled devices. I posted on page 2 of this thread (here) with an explanation of why. The Serial Protocol Communication whitepaper also explains the design choice.
Incidentally, the LV86 installer will place the files in the latest version of LV installed on your computer. When you open the VIs or use them on a block diagram in LV2009, they'll be recompiled to LV2009 automatically.
I would like to use I2C interface with a 6221. The requirement of the library "IDW" is that the device must support "per-cycle tri-stating" like 655x. Could somebody tell me what it means? How can I make some changes to my device to fulfill this requirement?
Hi Senmeis -
Here's the Help article on per-cycle tristate: http://zone.ni.com/reference/en-XX/help/370520K-01
And here's an article on Hardware Compare, which is the primary motivation for having per-cycle tristate: http://zone.ni.com/devzone/cda/tut/p/id/7281
Unfortunately, this is a feature of the I/O buffers designed onto the device, and so there is no modification that can be made to a 6221 to give it tristate capability.
Using LV8.5 and trying to implement I2C with DAQmx, is there any reason why a PXI-6534 won't work?
http://zone.ni.com/devzone/cda/epd/p/id/6200#h42 Specifically calls out 6535/6/7; is there a reason the 6534 was omitted from that list? The PXI-6534 has a clock.
Hi Raj -
The main reason the 6533/4 isn't supported for any of these libraries (SDW, IDW, JDW) is the lack of a Data Active event. Without that event, the input and output tasks aren't synchronized. This was discussed on the SDW forum: http://forums.ni.com/ni/board/message?board.id=Com
Additionally, the IDW library specifically requires per-cycle tristating on the I/O buffers. The 6534's buffers must be set to tristate by a software call, not by a value of 'Z' in the waveform data. Only the 6547/8 and 6551/2 have per-cycle tristating.
David S., from Systems Engineer, CLD wrote:
"If you send a NACK to the slave device, the master is controlling the SDA line. It doesn't make sense to listen to that line with a compare sample, since you already know its value will be Z when the master sends NACK. It only makes sense to compare the line's state against an expected value when the slave is sending ACK/NACK. In this situation, choose the Listen ACK or Listen NACK state for that VI. If you look at the IDW Transmit - Multi Byte example, you can see that I'm listening for an ACK from the slave in every byte. This inserts an "L" sample into every ACK bit, as expected."
I am trying to generate a waveform with the device NI PXI 6551.
The problem is the device won't generate anything because of this particular L inserted; il only accepts Z, 1 and 0.
Then, I would like to understand how inserting an L in the waveform makes it possible for the slave device to send an ACK, and for us to listen to this ACK.
Thank you for your answer,
Hi Johanna -
Take a look at the examples in the Serial Protocol Communication reference design. They show you how to configure your device properly to be able to communicate over I2C.
I'm trying to read/write an eeprom with an i2c protocol and ni pxi 6551 module.
At first, I tried to simply read the eeprom, because i know i am expecting 11111111 as a response, but it did not work.
So I tried something easier, and I succesfully wrote a pcf8574ap.
But i can't read it.
Seems like I am not able to "hear" the answer; when the sda line should be filled with an 8bit information, it remains at Z-state.
And because I am using the i2c library, i think there might be a problem with this library, or i am doing something wrong.
Hoping someone has an answer.