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lion-o
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Re: CLIP Node XML Generator (CXG)

[ Edited ]

Hey David,

 

I think there's a bug in the XML generation. In the created XML, the <HDLName> within the <CLIPDeclaration> is always set as the name of the VHD file. It should however be set to the top-level entity name as chosen by the user in screen 1.

 

Regards, 

Message Edited by lion-o on 05-13-2010 02:14 PM
Mike Lyons
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cris2per
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Re: CLIP Node XML Generator (CXG)

Is there any XML generator for file name from a folder?

 

 

Is there such program/application that can generate XML from a folder? For example: I have a folder of photos, and I'm going to use those photos for my gallery which uses XML. My problem is too many photos to handle... is there any solution for this?

 

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MG-ESA
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Re: CLIP Node XML Generator (CXG)

Hi...I have dowloaded the  XML Generator (CXG) application from the site.I was trying to use it with a counter but after the first window, when I put the signal and their properties(type....) the windows goes in block and I can't do anything...only move the window...why?

Thank you...


Christian L wrote:

Please provide feedback, comments, and questions on A XML File Generator for LabVIEW FPGA CLIP in this thread.

 

- David

 

(posted by Christian on behalf of David)

 

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vakost
Posts: 9
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Re: CLIP Node XML Generator (CXG)

Hello.

 

I have a question, things are very unclear yet for me in the labview FPGA and I am trying to understand some basic functionality.

 

The CXG is now embedded in the FPGA properties -> Complenent Level IP ??

 

I was running labview 8.6 and when I went to 2010 the Component Level IP was upgraded with many more properties and it can generate the XML file needed.

 

So, is this XML file the one I am going to use or should I also use the CXG?

 

Thanks a lot,

Bill.

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plist
Posts: 9
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Re: CLIP Node XML Generator (CXG)

Should I be able to use this in combination with a programmatic build VI in order to dynamicaly update the CLIP node and recompile my FPGA bitfile? Assuming the I/O does not change, but only parameters inside of it, that is.

Basically I'm developing a VeriStand custom device that uses an FPGA. I want to not have the end-user need to open LabVIEW, only VeriStand. As they will not be changing the I/O of their HDL, only the logic inside of it.

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