From Friday, April 19th (11:00 PM CDT) through Saturday, April 20th (2:00 PM CDT), 2024, ni.com will undergo system upgrades that may result in temporary service interruption.

We appreciate your patience as we improve our online experience.

Multisim and Ultiboard

cancel
Showing results for 
Search instead for 
Did you mean: 

placement of component

Solved!
Go to solution
hi......
i have the problem of placement of single not out of 6 not gates in CMOS_5V (4069BCL_5V)...
i want only one not gate in my circuit...and i selected A not gate.....and press k...
after that when i'm simulating i'm getting simulation error...
when i'm selecting not gate IC , i'm viewing only one not gate instead of IC...
so i dont know what is the problem...
so please help me
0 Kudos
Message 1 of 3
(3,539 Views)

Hi there,

 

Did you place a VDD and VSS connector on the same page as the gate? Please post your file if you are having difficulties.

 

Thanks!

----------
Yi
Software Developer
National Instruments - Electronics Workbench Group
0 Kudos
Message 2 of 3
(3,531 Views)
Solution
Accepted by topic author ellendula
hi...
thanks for ur reply...
i got solution for the problem....
0 Kudos
Message 3 of 3
(3,529 Views)