multisim

[NavidG]

Thanks for reply Jeff but the attachment is just an image file ( .png), it is not a schematic.

Navid

[jcham]

Hi Navid,

It is actually a Multisim snippet file, this uses the PNG extension. These can be dragged and dropped into Multisim and are a great way to share components or circuit snippets. 

I forgot which version you were using and accidentally attached the 14.0 version though. Here is a file that will work with Multisim 13.0.

As mentioned above, just drag the file into Multisim or use the File>Snippets>Open snippet file... option. 

Jeff

National Instruments

[NavidG]

Thanks Jeff. I simulated the circuit for inverting unity gain for u1 ( schematic attached here), and the simulation results are again garbage same as what I had before( output saturates for 1Khz 20mv input signal). I checked with Apex and they said the model is working in other simulator like LT Spice. I am not sure what is wrong here.

Thanks

Navid

[NavidG]

Hi Jeff,

By looking at Spice netlist generated by Multisim, I see that your component connections are not right as I guessed. I have attached a test  circuit schematic with your PA96 you gave me today. For example, I see RL in spice netlist is between nodes 1 and u1_out where it should be between 1(u1_out) and 2. Or, Cc is between 3 and 5 where it should be between 7 and 8. Please help.

[jcham]

The connections are correct, please see below. 

In the netlist, the numbers next to Cc, for example, refer to the net connections:

*## Multisim Component Cc1 ##*
cCc1 3 5 1.5e-010

The means that Cc1 is connected between nets 3 and 5. 

On the connection for PA96, we see the following:

*## Multisim Component U1 ##*
xU1 0 2 1 u1_out VCC VEE 5 3 PA96_3__APAMP__1

Here you can see that that nets 3 and 5 are connected to the final two nodes on U1. 

From the .subckt declarion for U1, you can see how these nodes are mapped:

**********
* REVISION 1 FEB 15 2007 INITIAL RELEASE
* SYMPOL PA85
* BEGIN MODEL PA96_3
* PINOUT ORDER +IN -IN CL OUT +V -V COMP COMP
* PINOUT ORDER    4    5   2      1      3   6       7         8
* NOTE THAT THIS MODEL DOES NOT PERFORM THE
* BANDWIDTH FALLOFF AT LOWER +SUPPLY VOLTAGE
* AS SHOWN IN THE DATA SHEET
.SUBCKT PA96_3__APAMP__1 4 5 2 1 3 6 7 8

The order on the .subckt line corresponds to the order seen above on the xU1 line. The final two nodes here are labeled 7 and 8, which we can see from the comment map to the two COMP pins.