identifying non-populated parts in schematic

[NavyJay]

Hi,

I'm wondering how I might add a part (capacitor in this case) to my schematic identified as an unpopulated part.  The part would not have a value or be inserted into the SPICE netlist.

-Jason

[lacy]

I believe this can be done, but you would need to try it. This is just off the top of my head at the moment .Try creating a part for layout only using the component wizard and don't assign any values to it. You can copy one of the symbols from the database for the symbol of this part. Also do not assign a footprint to it. This will make it a virtual component and will not (hopefully) be transfered to Ultiboard.

I hope I have understood what you need and I hope this works. Let me know if it doesn't and I will examine it further.

[MichaelWebster]

In my limited experience, usually you want the no-pop part to transfer to layout.  I've generally used it in cases where I'm not 100% sure whether I'll need that second bypass cap or whether the PWM on our micro is going to need a pulldown.  So I want the pads to be there as backup so we don't have to respin the board, but I don't want a part on the BOM or in my simulation netlist until I figure out whether they're really necessary or not.

That being said, we don't use Ultiboard for layout, so I don't know the answer to the original question ... sorry.

[NavyJay]

Hi Lacy,

Thanks for the reply.  A virtual component will still be simulated as a component in the SPICE netlist, but I did find a solution.  In the component Properties box, select the Variant tab and change the status to Excluded.  This grays out the component in the schematic view and removes it from the simulated netlist.  I'm not sure if this also removes the part from Ultiboard, but I use PADS for layout.

-Jay

[lacy]

Great to see you found a better solution. I had forgot about the variant manager since I have rarely had a case to use it. As far as tranfer I would have to test it to be sure, but I do believe it will exclude it from export at least to Ultiboard unless it is the active varient at the time of transfer.

Just a quick note. If you create a blank component with no model it will not simulate and should not effect the netlist as it would appear more or less invisible to the simulator. It would treat such a component as an open circuit. I thought you might want to know this information just for reference.

Message Edited by lacy on 08-06-2008 05:06 PM