convergence error in mosfet driver NCP5355D circuit, might be bootstrap mistake?

[wliiii]

Hi there,

I'm using the Multisim 13.0.1. There's a 8-pin mosfet driver NCP5355D available in the library. I wanted to use it for switching half-bridge MOSFETs, but a simulation error has occured. The report said that 'Transient time point calculation did not converge'.

I've included the circuit with the gate driver, and also the circuit with separate pulsed voltage sources for switching MOSFETs, which could provide a general view of what I intended to achieve with the gate driver.

I also tried to configure the gate driver step by step- I started from the VS, CO, EN, PGND pins side and got no simulation errors then; but when I started connecting the BST and DRN pins, convergence error occurred. So is the convergence error resulting from any mistakes in connecting the BST and DRN pins?

To make it easier, the datasheet of NCP5355D is also attached here, where example application connections are included.

Expecting your insights and thanks in advance!

[johnsold · Accepted solution]

I do not have Multisim so I cannot see your circuits but have some general observations.

1. MOSFET driver models often use switches and these can lead to convergence problems. This is because the switching action introduces a strong non-linearity into the model.  I wrote my own model using transmission lines for delay and non-linear dependent sources with tanh functions rather than hard switches.

2. If you do not need to model the detailed behavior of the driver, using pulsed sources with rise/fall times as long as possible without changing the behavior of the MOSFETs might be a better choice.

3. There are books written on how to deal with SPICE convergence problems. This is what I found helpful from one of them:

** From Inside Spice by Kielkowski
**   Convergence aids:
**     Select appropriate RELTOL
**     set VNTOL = RELTOL*Vsmall
**     set ABSTOL = RELTOL*Ismall
**     set GMIN = 1/Rp where Rp is parasitic resistance which
***      will have minimal effect when added to circuit.
**     semiconductor models should have non-zero resistances
**        RS (diode), RE, RC (BJT), RD, RS (FET)
**     Raise ITL1=500 (DC OP iterations limit)
**     use .NODESET
**     use source stepping ITL6=500
**  Transient convergence aids
**     Add capacitance to device models:
**        CJO (diode), CJE, CJC, CJS (BJT), CDG, CGS (JFET)
**        CGDO, CGSO, CGBO, CBD, CBS, CJ, CJSW
**     increase ITL4=40
*

Good luck.

Lynn

[wliiii]

Hi Lynn,

Thanks a lot for your reply 😃 I was also considering about using pulsed voltages as switch controls and edit the deadtime into the voltage source configuration. On the other hand I also would love to apply the gate drivers in the circuit which helps make the circuit simpler and compact.

Best regards.

[wliiii]

Hi Lynn, 

I checked the Multisim help and there's a specific subject about Convergence where the Simulator Adjustment Recommendations is given.

Suggested values for ABSTOL, VNTOL, RELTOL are not above 1e-8A, 1e-4V, and 0.01 respectively. I tried these and the convergence error disappeared to a certain extent - unexpectedly the convergence error occured again at about 450ms. Anyway thanks a lot for your suggestion. I think there might be some unfavorable connections or values in the circuit itself. If you happen to have access to Multisim and could check the circuit out, it would be really great.

Hereby I attach a screenshot of the circuit with gate driver, may I ask if you have any ideas about the possible mistake in it? FYI, I ran the transient simulation of the current in L1, it seems that the current in the inductor does not converge at all. Its current has a stair-like increase.

[johnsold]

I do not have Multisim.

I see a few things which might be factors.

The bootstrap capacitor might be small for a 500 Hz pulse rate. I do not have time to look up the data sheets and calculate the required currents. 0.2 uF is probably OK for 50 kHz but may be small for 500 Hz.

Stair-like increase in current in the inductor might be due to the fact the the resonant frequency of the L1 C2 circuit is 159 kHz and you are driving it at 500 Hz. It might also be due to the bootstrap capacitor being too small.

Simulations are design tools intended to verify that a preliminary design works as expected. Often they are not very good at modelling the behavior of poor designs.  Things like calculating the bootstrap capacitor for a particular operating frequency need to be done manually to select a value appropriate to the requirements before simulation.  When a circuit does not work in simulation as you expect, it can be helpful to model one section at a time. For example to validate the bootstrap capacitor model just the gate driver and capacitor with the transistors removed. Use resistive loads or simple capacitors in place of the gates. Maybe a voltage source at DRN terminal. 

The load values look more like an academic execise than some realistic load. What are you trying to do? Model the outuut behavior? The behavior of the transistors? Or the behavior of the gate driver?

Lynn