VHDL reference components from Digilent

[evandrorech]

Hi! I'm using Multisim 13 to configure a Nexys2 board from Digilent. For now, I can do this using only the standard PLD components from Multisim.

Digilent provided in the Nexys2 page some reference components, from simple applications (like PWM) to more complex (like VGA), and I want to import they to Multisim:

http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,789&Prod=NEXYS2

I know I probably will need to adapt some signals (like vectors) in the VHDL, but in addition I'm trying to import the component in Multisim, and in the step 5 of the component wizard, I need to describe the spice model. There's a way to convert the original VHDL component to a spice model, create a PLD model without the spice simulation model or use a dummy model to skip that step?

Thanks!

Evandro Rech

[lferreira]

Hi Evandro,

Have you ever seen below link that describes Program Xilinx PLD from the Multisim Environment?

https://decibel.ni.com/content/docs/DOC-31250

http://www.ni.com/white-paper/14871/en/

http://www.ni.com/tutorial/3173/en/

http://www.ni.com/tutorial/12266/en/

http://www.ni.com/white-paper/14871/en/

Thanks

[evandrorech]

Thanks for the response, lferreira!

I am familiar with these articles! I read they to develop some simple circuits to my Nexys2, now I'm thinking if it is possible to create my own PLD component, but without the spice model. I know how create components using his spice model and the VHDL to export, but the components in the Digilent site and in other files from internet are only described in VHDL code, I don't have the spice model for simulation.

I see three possible solutions and would like to know if any is achievable:

1. Convert the VHDL model of the component in a spice model to be able to simulate;

2. Create the component only with the VHDL model to export, without the spice model;

3. Create the component using a dummy spice model, with no function and no simulation, only terminals without description, but possible to compile in a VHDL file.

Thanks again!

Evandro Rech