Problem with keepout area 10.1.1

[david_c_partridge]

I have design that uses a two pin header to provide power to the board.  The board is a four layer board with ground and power on the inner planes.

I wanted the Vcc supply connection on the header to NOT connect to the inner power place directly through the header mounting hole, but to run a track on the top layer to the decoupling capacitor nearby which does have vias to the power planes.

I though that was not a problem - just put a keep out area under the header part for the Power net group.

That works, but I always get a DRC:

Netlist and DRC check [Frequency Divider 2]  <2010-03-15 15:45:44>
    Design Rule Error: The object "Pad: Type(THT) Name(2) Part(J7) Clearance(1.0000 mil) Net(VCC) Hole(39.3701 mil) " is within a keep-out area for net group : Power.
Netlist and DRC check completed;  1 error(s), 0 warning(s), 0 Filtered Error(s);  Time: 0:00.34

The only way I found was to put a trace down on the relevant layer all round the header, and then use Copper Delete/Copper Island which I knew from previous experience was likely to cause problems, and also leaves a spurious track in the layer.

I realise I could just filter the error, but if I do that, when I go to Export the Gerbers, Ultiboard still complains that there are outstanding errors.

Thanks

Dave

[GarretF]

I put together a little example to show my understanding of the problem. I assume you are getting the DRC error because you are running VCC into the keep out area, and VCC is in the Power group. As you've described it, I think this should also give you a connectivity error because the header would not be connected to the power plane (Ultiboard doesn't allow connections through components), so all parts of VCC would not be connected together.

So, I think the correct solution is to create a new net, say VCCHEADER, that is the connection between the header and decoupling capacitor. VCCHEADER would not be in the Power group so it can enter the keep out area. I put an example of this in the file as "keepoutfixed." I think this also make logical sense because they are really separate nets in your design. This would also solve any connectivity errors.

[david_c_partridge]

I cannot open the project which you attached, as it was for Ultiboard 11 which I don't have.

In a sense you are right, the PTH for the header pin is in net VCC, and it is complaining about that, even though I restricted the keepout to net group Power and to the plane which has VCC in it.

I don't think I can create a new net as the proposed new net (VCCHEADER) would connect to the +ve terminal of the capacitor, which is of course directly connected to VCC, and the two nets would become one.

Or are you about to hit me with a "slap head" (DOH!) moment?

Thanks

Dave

[GarretF]

I "converted" the file to 10.1 so you can see it. If this doesn't explain the solution, could you post a simple example with the problem your having because then I don't think I understand the problem? (Maybe I need a slap head moment too)

[david_c_partridge]

Here are two projects as I couldn't work out how to copy a complete design within a project (how do you do that)

One shows the problem, and other shows how I used a trace on the power plane and delete island to resolve it.

[GarretF · Accepted solution]

HI David,

It was me that needed the moment. Now that I understand the problem, I can say I don't have a better solution for you. I'll add a bug so that the export warning message does not appear for DRC errors that have been filtered, which would solve part of the problem.