Multisim and Ultiboard

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Is there a valid way that running a simulation could use up all memory?

I say no.  But then I just read a response in a thread which said something about making an interactive simulation setting such that memory isn't saved.  The flip side of this is that it is believed memory should be saved for some reason, which says it is possible that memory can be exhausted.

 

The reason I ask this question is I ran a simulation for about three days, but before the simulation got to where I wanted it, Multisim shut down because my system ran out of memory, or so said the little "Out of memory!" window I got in the center of the simulation when I checked in the morning.  I concluded that Multisim has a memory leak, for as I see it, no circuit simulation should ever cause an out of memory error.  Rather, as I saw it, data is generated, and then that data is discarded for new data which replaces the old.  Hence, it is up to the user to save things periodically either manually or by setting up some form of an automatic save.  Granted, as of this moment, I know not how such an automatic save loop might be generated in Multisim, and I'll take whatever suggestions others may have.  

 

So am I wrong about this?  Is there some way that a circuit simulation can, in fact, use all of memory, besides a memory leak, with interactive simulation settings such that the data isn't saved in order to conserve memory usage?   

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Hi Eulers,

 

I am not sure but this KB may describe what's happening.

 http://digital.ni.com/public.nsf/allkb/E7EC0475F3B2022F8625741A006B4879

Tien P.

National Instruments
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Tien,

 

As I understand that hotfix, it's addressing a leak that may come about through the XP theme setting and that the workaround is to change to the classic theme.  I've always run XP using the classic theme, therefore including when I ran out of memory.

 

Here's what I think happened, and if this is the case then I see no cause for further alarm:

 

The circuit was a PLL frequency synthesizer.  By its nature this is complex, for there are both analog and digital aspects and they interact continuously making the calculations laborious.  Moreover, the setting was "set to zero," for in the beginning the output of the loop filter must rise from rest -- one can't just jump ahead in other words.  Then I later found there was a bug in my logic that determined the fed back frequency.  That bug, though small, caused many more permutations than were necessary for the synthesizer to lock.  Due to these permutations (and I say this as best as I know how,) many more objects were created than were necessary, objects that couldn't be destroyed because they were still needed for determination of the overall solution.  Eventually this continuous creation of these objects caused my machine to run out of memory trying to solve the circuit.  In other words, the fault was not Multisim but rather was an incorrect circuit design that caused Multisim to work much harder than was necessary.

 

My evidence that causes me to draw this conclusion is that, after removing the logic bug, the PLL synthesizer did eventually lock -- the output of the loop filter did eventually converge to a narrowly varying voltage.  The simulation did take some time to run, true, but it was only a few hours not days.

 

   

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