Bugs? (My) errors?

[willyp86]

Bugs? Errors? Human errors?

I tried the new multisim 11 with a new project. Since i`m experienced with multisim 10.1, i see that this new version is improved in many ways, great!

However i`m facing with some serious problems that, at the moment, block my whole design.

Here it is:

Question A:

Is it valid to use a schematic, lets say a LED driver schematic, multiple times throughout the design?

For example, i have the main design and lets call this:(1) and have the led driver schematic and lets call this: (2).
Is it valid to add from schematic (1) the schematic (2) multiple times by the "add hierarchical block"?

Problems in A:

The LED driver is a chain serial port. This means that from HB1 (the led driver) I need the output connector(SDO-SerialDataOut) connected to HB2(the clone led driver again) to its input connector (SDI-SerialDataIn).

This gives me warning messages every-time i use CNTRL+Z throughout the design (very frustrating!) that there are merged net names used **SEE FIGURE**.

I fixed this by assigning a manual name to the net.

Above popup caused by example below

(note below gives a popup about SDO/SDI. not the above msg VS-GND):

 Next problem:

For this problem i need to tell that i didn't set up any "renumber parts" in the renumber menu option. I just pick components and place them.
In this problem the same situation applies: we have the main(1) and multiple (2)ledbars.

In the my Ledbar schematic I'm using optocouplers, packaged as 4x in 1 single IC. There is a neat function in multisim that gives me the opportunity to place 4 components with the same number but different alphabet letter to show that they are in the same package. (eg. Uc3A-Uc3B-Uc3C-Uc3D).

Now it continuously happens that whenever i use CNTRL+Z again in the design, multisim automatically renumber these 4in1 components to separate components. So the original (Uc3A-Uc3B-Uc3C-Uc3D) will be (Uc3A-Uc4B-Uc5C-Uc6D).

Since this happens without knowing I usually see this when i`m already in Ultiboad, then I suddenly see 4 components instead of just 1. And if i try to change it to the correct number (by using the replace option in the properties menu of the component) then i can select the correct number (in this case Uc4b --> Uc3b) but after clicking not always the component changes happens. It just stays at number Uc4b. And IF it does change to the correct number, a CNTRL+Z just re-renumbers them and i`m back to where i`m started.

Btw. This must be a bug in the software i think, because even in an empty sheet with a subpage OR HB you can see this happening directly. Just add the TLP521-4 as U1A-U1B....... and make it a subcircuit or HB. Now do something in the "main" design... place a wire for example (double clicking mouse on the drawing space) and undo it after drawing. You directly see after undo-ing that the subcircuit has changed.

Example pics:

This is how you want the design:

This happens after doing a undo@ the parent page

Next Problem:

This is really my biggest problem. I have components of 64I/O's placed in a bus and that multiple times since it is again a HB. Now i just see that everything in the busses was renamed :(:(.

I mean, i have from the HB a bus to the outside where I connect other stuff to the bus. So from again in the above example, from (1) I have a bus from (2) where i connect different componens available in (1) to the bus from (2). Now it happened that my IC-nets inside the (2) schematic is complely renamed. So now if i check the names in the bus, i see the original names (connected to parts @(1)) and i see all of the I/O's from IC @schematic (2) that are all renamed and not anymore connected to the components of (1)**see figure below** where you can see the original names (in the image "Led1,led2, barled,...) and the new netnames ( in the image 14,15,16,17) that where somehow automatically created and connected to the bars.

This means I have to do all of the I/O's over again. What am i doing wrong? I think the problem lies in the project management design. Whenever i click (@multisim) on a schematic file that is placed inside the project three, it will open just"as is" not as a parent of the main circuit and so using his own numbers for the components.

Final:

I really hope someone knows a solution for me. I`m now using the trial of MS 11 downloaded from this website.

Message Edited by willyp86 on 02-09-2010 02:27 PM

Message Edited by willyp86 on 02-09-2010 02:28 PM

[clansing]

Hi,

I was looking at the net and bus parts of your questions.

To answer your first question, yes you absolutely should be able to use a hierarchical block multiple times like that in a single design. Whenever you connect two nets together (such as when joining two hierarchical blocks in your example), Multisim is supposed to remember which name you wanted the first time it asks and not ask again until there is a possible change to the name (such as connecting more existing nets to it, or disconnecting then reconnecting the nets).

Is it possible for you to attach the actual design files or at least a sample of a design where you are having the problem with the net name conflicts so we can find out exactly what's causing this in your case?

For the buses, it's hard to say without seeing how they got to that state, but one thing I can suggest is that if you already had a bus set up inside the block, and a bus set up outside the block, when you connected those buses together through the bus IO port Multisim should have prompted you to merge the buses. There is an option at that point to automatically connect the bus lines together, but can it only do that if the bus line names are already the same on the two buses. If one bus has lines (1, 2, 3) and you want to connect it to a bus with lines (Led1, Led2, Led3) for example, you need to manually select how the lines should be matched (which you can also do when connecting the buses) because Multisim doesn't know if you mean to connect the lines together, or if you want a 6 line bus, or something in between. But without knowing the initial state I can only guess...

[willyp86]

Thanks for your responce.

 I would like to reply on your message about the busses:

Since the past days I did quite a lot of thinks and didn't had any errors with it. So i think that it was caused because I opened the HB directly, instead by using the "edit" button in the main page. This happened because I created a Multisim project and added all the multisim files to it and then opened it from the project window.

I did not test this yet, but when I have some time, I will see if that will reproduce the problem

About the problem four in one opto-coupler, this is very easy to reproduce. Today I reinstalled MS trial again on another PC and there I had the same error again. So i`m sure that it must be an bug inside the software. I fixed it for now by manually creating a new component that is just one package instead of 4 seperate items for the same IC.

[willyp86]

Is there no one who can at least confirm bug #2 listed above???

[clansing]

Hi,

We have been able to reproduce this. It does look like the undo is affecting the RefDeses in hierarchical blocks and subcircuits - which is not the correct behaviour. This is a complicated problem, but we are working on a fix for it, and should have it addressed by the next release.

[muks]

Can you post the car number?

[willyp86]

Car number?? And is there any news when the next release will be out?

Message Edited by willyp86 on 02-18-2010 08:42 AM

[clansing]

Hi,

The tracking number on that issue is 116867. Unfortunately we are not able to discuss release plans, so there isn't anything I can say about scheduling for any future releases, patches or updates.