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On a 4-layer design with only through-hole vias I'm running in a problem where I didn't find any solution.
I have to place a through-hole vias, which for some reasons has to pass a big/large trace in one of the inner layers. How can I prevent Ultisim 10.1 from connecting the vias to this trace in the inner layer?
Or is there any method for sparing out parts of a trace?
If you place a via over a trace it will short, here are two suggestions you can try:1. Place a copper area under the via, void around the via will be create and you can run your trace to the copper area.2. Double click on a via and select the Layer Settings tab, uncheck the copper ring layer that the trace is on. If you use this method, please double check with your manufacture, my concern is if the via is a plated it may short to the trace anyway.
