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main circuit not found in spice netlist

Hi all,

 

I'm trying to import a .cir file for vishay 6N137, however I keep getting the error main circuit not found in spice netlist.  Does anyone know what is wrong with the spice file?  I've pasted it below.

 

** Spice3 Model **
**  --  6n137,VO2601/11, VO0600/01/11 ---
**  High speed 10 Mbd, NMOS output, enable- high
**  12/02/2009 mfc
**
** test conditions:VCC=5V, RL=350, CL=15pF, IF=10mA
** characteristics: VF=1.4V, ITH=5mA, VEH=2V, VEL=0.8V
** VOL=0.6V, tpLH=TpHL=70nS, tr=22nS, tf=17nS
**
** Model Node - Symbol - Pin
** 1 (DA)       A          2
** 2 (DK)       K          3
** 3 (GND)    GND          5
** 4 (VO)       VO         6
** 5 (VE)       VE         7
** 6 (VCC)    VCC          8
***************************************************************
.SUBCKT 6N137  DA DK GND VO VE VCC
DD1 DA 6         DEMIT
vV1 6 DK  DC 0
hH1 1 GND vV1 600  ;5mA -> 3.0V

AU1.A  [1] [DU1.A]           ADC_A
AU1    [DU1.C DU1.A] [DU1.Y] XBUF_H   ;DIGITAL BUF WITH CTL
AU1.C  [VE] [DU1.C]          ADC_C
AU1.Y  [DU1.Y] [2]           DAC_Y

R1 2 5 1K
R3 VCC VE 6.4K
**QQ1 VO 5 GND Q_NPN          ;OC OUTPUT
XQ1 VO 5 GND Q_NMOS           ;NMOS OUTPUT

.MODEL    DEMIT   D
+IS=1.69341E-12 RS=2.5 N=2.4  XTI=4
+EG=1.52436 CJO=1.80001E-11 VJ=0.75 M=0.5 FC=0.5

.MODEL Q_NPN  NPN
+ IS=100P BF=100 NF=1.0 BR=1.0 TF=0 TR=0 CJE=1P CJC=1P CJS=1P VAF=1.0E30

.SUBCKT Q_NMOS 1 2 3
CGS  2 3 12E-12
CGD  1 2 6E-12
M1 1 2 3 3 MOST1 W=9.7M L=2U
.MODEL MOST1 NMOS(LEVEL=3 KP=25U VTO=2 RD=45)
.ENDS

.MODEL XBUF_H D_CHIP ( BEHAVIOUR= "
+; BUFFER W/ H-ENABLE 3-STATE CONTROL, 100 NS L-H(RISE) H-L(FALL) DELAY
+/INPUTS C A
+/OUTPUTS Y
+/TABLE 2
+; C  A  Y
+  L  X  Z
+  H  X  A
+/DELAY 1
+;INPUT OUTPUT RISE_DELAY FALL_DELAY
+   A     Y        50N       50N
+/CONDITIONAL_DELAY 4
+;EVENT TO CONDITION OUTPUT MIN/MAX TIME
+   ZH  C   (C=L)    Y     MAX     0
+   ZL  C   (C=L)    Y     MAX     0
+   HZ  C   (C=H)    Y     MAX     0
+   LZ  C   (C=H)    Y     MAX     0
+")
 
.MODEL ADC_A ADC_BRIDGE (IN_LOW= 2.8 IN_HIGH = 3.0 )
.MODEL ADC_C ADC_BRIDGE (IN_LOW= 0.8 IN_HIGH = 2.0 )
.MODEL DAC_Y DAC_BRIDGE (OUT_LOW= 0 OUT_HIGH = 4.0 OUT_UNDEF = 0)

.ENDS 6N137

**==================================================================*
* Note:                                                             *
* Altough models can be a useful tool in evaluating device          *
* performance, they cannot model exact device performance           *
* under all conditions, nor are they intended to replace            *
* breadboarding for final verification!                             *
*                                                                   *
* Models provided by VISHAY Semiconductors GmbH are not             *
* as fully representing all of the specifications and operating     *
* characteristics of the semiconductor product to which the         *
* model relates.                                                    *
* The models describe the characteristics of typical devices.       *
* In all cases, the current data sheet information for a given      *
* device is the final design guideline and the only actual          *
* performance specification.                                        *
* VISHAY Semiconductors does not assume any liability arising       *
* from the model use. VISHAY Semiconductors reserves the right to   *
* change models without prior notice.                    *
**==================================================================*

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Message 1 of 6
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Hi,

 

I looked through the model and I don't see anything wrong with it, maybe you can post your Multisim circuit.

Tien P.

National Instruments
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Message 2 of 6
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Do I need to add anything else?  I tried to import the .cir file without anything else in the schematic is that a problem?

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Message 3 of 6
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This netlist is a model and you can use it to create a component, refer to this tutorial to learn how:

http://www.ni.com/white-paper/3173/en/

Tien P.

National Instruments
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Message 4 of 6
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Hi everyone!

I am having the same problem with this spice code

I follwed the instructions in the NI Whitepaper www.ni.com/white-paper/3173/en/

 

Can anybode help? Thank you very much

 

* AMP04 SPICE Macro-model
* Description: Amplifier
* Generic Desc: BiPolar, InAmp, LoPwr, single supply
* Developed by: JCB / PMI
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 ( 05/1994)
* Copyright 1994, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.h... for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
* Rgain1
* | IN-
* | | IN+
* | | | V-
* | | | | REF
* | | | | | Vout
* | | | | | | V+
* | | | | | | | Rgain2
* | | | | | | | |
.SUBCKT AMP04 1 2 3 4 5 6 7 8
*
* INPUT STAGE
*
R1 2 9 2E3
R2 9 11 2E9
R3 11 12 2E9
R4 3 12 2E3
IB1 2 98 22E-9
IB2 3 98 21E-9
VOS 12 13 25E-6
D1 9 10 DY
D2 1 10 DY
D3 12 14 DY
D4 8 14 DY
*
* 1ST AMP GAIN STAGE, POLE AT 0.44 HZ
*
EREF 98 0 (60,0) 1
G1 98 15 9 1 1E-3
R5 98 15 1E9
C1 98 15 362E-12
* SECOND POLE AT 1 MHZ
G3 98 16 15 98 1E-6
R6 98 16 1E6
C2 98 16 159E-15
* OUTPUT STAGE
E2 22 98 16 98 1
R14 22 1 200
*
* 2ND AMP GAIN STAGE, POLE AT 0.44 HZ
*
G2 98 17 13 23 1E-3
R7 98 17 1E9
C3 98 17 362E-12
* SECOND POLE AT 1 MHZ
G4 98 18 17 98 1E-6
R8 98 18 1E6
C4 98 18 159E-15
* CMRR STAGE
E1 98 19 POLY(2) (2,98) (3,98) 0 5 5
R9 19 20 1E6
R10 20 98 1
* OUTPUT STAGE
E3 21 98 18 98 1
R11 21 8 11E3
R12 21 23 11E3
R13 23 5 100.2E3
*
* OUTPUT AMPLIFIER INPUT STAGE & POLE AT 10 KHZ
*
R15 29 4 5.16E3
R16 28 4 5.16E3
I1 7 30 10UA
EOS 27 3 POLY(1) 20 98 30E-6 1
Q1 29 8 30 QX
Q2 28 27 30 QX
R20 8 6 100.2E3
CIN 28 29 20E-12
*
* SECOND GAIN STAGE AND SLEW CLAMP
*
R71 31 98 1E6
G71 98 31 28 29 48.2E-6
D30 31 32 DX
D40 33 31 DX
E10 7 32 POLY(1) 7 98 -0.5 1
E20 33 4 POLY(1) 98 4 -0.5 1
*
* OUTPUT STAGE
*
RS1 7 60 1E6
RS2 60 4 1E6
ISY 7 4 0.124E-3
*
G7 34 36 31 98 5.5E-06
V3 35 4 DC 6
D7 36 35 DX
VB2 34 4 1.6
R22 37 36 1E3
R23 38 36 500
C6 37 6 50E-12
C7 38 39 50E-12
M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9
M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9
D8 39 47 DX
D9 47 45 DX
Q3 39 40 41 QPA 8
VB 7 40 DC 0.761
R24 7 41 375
Q4 41 7 43 QNA 1
R25 7 43 50
Q5 43 39 6 QNA 20
Q6 46 45 6 QPA 20
R26 46 4 23
Q7 36 46 4 QNA 1
M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9
*
.MODEL QNA NPN(BF=253)
.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8
+ LD=1.48E-6 WD=1E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5
+ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 CJ=0 L=9E-6 W=2000E-6)
.MODEL QPA PNP(BF=61.5)
.MODEL QX PNP(BF=12500)
.MODEL DX D
.MODEL DY D(BV=6.0)
.ENDS

 

 

 

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Message 5 of 6
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HI FRoloff,

 

Which part of the tutorial are you having trouble with?

Tien P.

National Instruments
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