Circuit Design Suite (Multisim, Ultiboard)

[HiZTrace]

In a recent design that included a component that had a thermal pad under the device that was connected to Gnd (Net 0) I encountered the following problems:

(Reference the attached photo)

When applying the power plane the scalloped edges occurred on the Pin 33 Pad due to the trace clearances, as shown in the left image, I do not want this extra material under the device, especially ground,

Changing the trace clearance is not an option and just changing the clearance on that pad does not solve the problem,

Adding a Keep-out area on the bottom layer appears to work initially, but creates a DRC error because the part itself is still within the keep-out area,

Creating a custom copper polygon the size of Pin 33 Pad does not work (as expected) because the power plane still creates the same scalloped edges,

Isolating the nets seemd to be a solution; 

So I changed the schematic to place Pin 33 Pad in Net 46 and left Pin 1 as Net 0

Then I created a net bridge from Net 0 to Net 46

Next I placed the net bridge between pin 1 and pin 33 Pad

This also created a DRC error because the Net bridge is located under the part

So I then changed the schematic to connect pin 1 and pin 33 Pad to their own net, net 46

Then I created a net bridge from net 0 to net 46 and placed it Outside of the part between net 0 Power Plane and net 46, and then placed a simple trace under the part connecting pin 1 to pin 33 Pad

This worked as shown on the right image in the photo (the net bridge is selected in yellow)

Is there a simpler solution to this problem? If not, there should be since more devices have ground or thermal pins under the device.

Michael

[dbur]

You should probably be placing a via array in the pad to make the connection to ground, otherwise the pad won't work as a thermal heat sink.

I don't usually do an area fill on the top like you are doing, but if you select the area/plane and go to properties/general you can set the copper area/plane clearance (not the pad or trace clearance) to a larger value and that will push the area fill back away from the pads.

Set the thermal relief for the area/plane to none and it will fill in around the vias you need for thermal heat sinking.

Here is a sample.  With clearance at 10 mils it had the same scalloping around the outer pins as yours.  With 20 mils clearance it's all cleared up.  Of course that will give more clearance everywhere else as well.  You can see my via array in the pad.  If you don't like having no thermal relief everywhere else you can select the vias and set them for no thermal relief instead.  You can actually build those into the part that way.