This looks to be because you do not have a net list. The netlist is generated from the schematic, so you won't have one if you are routing manually. Although you can edit the netlist manually, you can hide the design rule layer so that the design errors don't show. You'll probably still get a warning when you go to export the finished PCB, but you can ignore this so long as you have no other design errors.
In the final count it doesn't matter whether you route with a pad or a via, but convention says that you should use a via. If you switch layers using the shortcut key then a via is automatically created for you. Since you are using SMD parts, you should spend a whiledeciding how small you want your vias, as they rapidly become the largets roadblock for dense SMD layouts. I suggest using a via with a 0.4mm hole and a 0.7mm pad as most PCB manufacturers can make this, and you can easily stack the vias in a pattern which allows routing to each pin.
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