Generic ADC spice

[laffer]

Hi all,

       I'm going to run simulation by using the generic 8-bit ADC in Multisim.  However, I have to change some parameters of this generic ADC to test performence in different cases. Here is the spice code of the ADC:

.subckt ADC8 vin vref+ vref- F0d F1d F2d F3d F4d F5d F6d F7d clk eoc PARAMS: conversion_time=1u
xU3 clk EOC_clk ONESHOT PARAMS: pulse_width={conversion_time}
a2 EOC_clk eoc DELAY
.model DELAY d_delay(rise_delay=2n fall_delay=2n)

a1 Vin [F0 F1 F2 F3 F4 F5 F6 F7] Vref+ Vref- ADC_core

**FFs
ab0 F0 ~EOC_clk DGND DGND F0d 100 FF
ab1 F1 ~EOC_clk DGND DGND F1d 101 FF
ab2 F2 ~EOC_clk DGND DGND F2d 102 FF
ab3 F3 ~EOC_clk DGND DGND F3d 103 FF
ab4 F4 ~EOC_clk DGND DGND F4d 104 FF
ab5 F5 ~EOC_clk DGND DGND F5d 105 FF
ab6 F6 ~EOC_clk DGND DGND F6d 106 FF
ab7 F7 ~EOC_clk DGND DGND F7d 107 FF

.MODEL ADC_core ew_nla2d( )
.MODEL FF d_dff(clk_delay=1n set_delay=1n reset_delay=1n ic=0 rise_delay=1n fall_delay=1n)

.subckt ONESHOT in out PARAMS: pulse_width=100n
aU8 in 4 DIGITAL_DELAY
aU7 4 2 NOT
aU6 [4 2] 9 AND2
aU5 in 1 NOT
aU3 [in 1] 6 AND2
aU2 U2_OPEN_S U2_OPEN_R U2_OPEN_CLK 6 9 out U2_OPEN_notQ SR_FF
.MODEL SR_FF d_SRff (clk_delay = 1n set_delay = 1n reset_delay= 1n ic = 0 rise_delay = 1n fall_delay = 1n)
.MODEL AND2 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT d_inverter (rise_delay = 10n fall_delay = 10n)
.model DIGITAL_DELAY d_delay (rise_delay={pulse_width} fall_delay={pulse_width} delay_type="transport")
.ends

           It's extremely helpful if someone can tell me what's meaning of the parameters. Like what's the ".model DELAY d_delay"? is it the  whole adc delay? And what is the ".model DIGITAL_DELAY d_delay"? Besides, could I know the structure(connections and gates) of this ADC?

Best Regards,

Laffer

[Tien_P]

Hi Laffer,

This model is based on XSPICE and not spice, you can download the manual and other resources from here:

http://users.ece.gatech.edu/mrichard/Xspice/

The ADC model is made up of various core parts such as AND gate, flip-flop gate etc... connected together to create ADC model.

Just to give you an idea, this section in the model:

a2 EOC_clk eoc DELAY
.model DELAY d_delay(rise_delay=2n fall_delay=2n)

Anything beginning with "a" is call function and it is calling a model name "Delay",  the 'EOC_clk' and 'eoc' are nodes connecting to the delay model.

The .model part is the model for the "delay