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Review my CLDs?

Hi Danielle,

 

this is muuuuuuuuuuch better!

 

You would still lose a point for not changing the default icon of the boiler status indicator type def control and maybe 1 for wires behind structures (there is one which goes behind a comment in one of the subvis). I can't spot anything else that would be obvious.

 

Btw the help print was not saved in the folder. Just double check at the end of the exam.

 

If we are making a pessimistic estimate for functionality of 8/15 I would very much assume that you got this one.

 

Let me know how it goes 🙂

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Thank you so much Mathis_B, I'll let you know!

 

Danielle

"Wisdom comes from experience. Experience is often a result of lack of wisdom.”
― Terry Pratchett
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OK, so first time I didn't pass, because I put too much time into documentation and style and didn't get just enough functionality points 😞

Second time I documented as I went and only put 1/2 an hour at the end for additional documentation (as you suggested) and I passed with flying colors!

 

Thanks all for your help!

Danielle

"Wisdom comes from experience. Experience is often a result of lack of wisdom.”
― Terry Pratchett
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Hi Danielle,

 

I'm so thrilled for you! It doesn't matter that it took two attempts. Rumor has it that the CLD has a fail rate of about 50%. It is probably the second hardest exam NI has to offer (after the CLED which I haven't taken yet) so big congratulations are in order for taking this hurdle. You have done brilliantly!

 

BR Mathis

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@Mathis_B wrote:

Hi Danielle,

 

I'm so thrilled for you! It doesn't matter that it took two attempts. Rumor has it that the CLD has a fail rate of about 50%. It is probably the second hardest exam NI has to offer (after the CLED which I haven't taken yet) so big congratulations are in order for taking this hurdle. You have done brilliantly!

 

BR Mathis


I thought the CLA was much worse than the CLD.

 

The CLED was just insane.  Imangine trying to do a CLD on an RT system and then a half CLD on a PC and FPGA.  And also make them all work together.  And it takes 20 minutes or so to compile your FPGA.  It is not for the faint of heart, especially when the sbRIO just goes into a permanent reset mode (like mine did).


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Personally I think that the CLA is not that difficult with the right preparation and the right strategy. The CLED is crazy as you have to throw everything overboard that you have started breathing with every fibre of your body when doing the CLD and CLA, which is: documentation, documentation, documentation. Even style isn't very important.

 

I've heard of people that have passed the exam not to even bother with it. 50% are for functionality, 30% design (which I interpret as architecture), 15% style and 5% documentation. That is such a major rethink of what we usually have to do ... crazy

 

btw. were you there last week in Austin?

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Mathis_B wrote:

btw. were you there last week in Austin?


I was not.  My 4 month old son told me I wasn't allowed to leave.


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@crossrulz wrote:

I was not.  My 4 month old son told me I wasn't allowed to leave.


Quite a talented 4 month old you have there, if he is already forming sentences.

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I let you get off this time 😉

 

There was an interesting talk about Arduino integration in LabVIEW. Would that be something for him 😉

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@Hooovahh wrote:

@crossrulz wrote:

I was not.  My 4 month old son told me I wasn't allowed to leave.


Quite a talented 4 month old you have there, if he is already forming sentences.


In a language that only his mother understands.


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