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Simplified XML Generation for FPGA Personalities

Status: New
by Member Chris Washington on ‎04-15-2011 10:07 AM

Benefit: Simplify the process and reduce errors when using FPGA personalities


Idea: Querry the user-generated FPGA diagram and automatically create the XML file.  Additionally, have some kind of editor/viewer for the XML file that would present the information similar to how it is presented in the System Explorer but allow the user to edit certain values (or just make it editable in the system explorer).  Some items would be read-only (items specific to the bitfile communication) and others would be editable (heirarchy, scaling, etc). 


Ultimately, the process for using FPGA Personalities would be:

 - create FPGA VI using NIVS interface/template

 - select interface in "utility/view" or System Explorer (XML file automatically generated)

 - edit default settings if desired


by Active Participant griffindore
on ‎04-15-2011 01:10 PM

Querying the FPGA diagram to generate the XML file is extremely difficult. I think a better solution would be to have a configuration based utility that would allow a user to specify the type of I/O (basic, advanced, or IP-based) and custom device components, and then the utility would script both the FPGA diagram and the XML.


This configuration based utility is used as the XML editor because it will script the XML. It can be used as the XML viewer by giving the ability to import an existing XML config. The possiblity for only editing the XML file and not re-scripting the FPGA VI should be included in case someone needs to customize the FPGA beyond what the tool can provide.


Process now becomes:

-run configuration tool to configure the type of I/O someone wants in their FPGA

-click generate to auto-generate the FPGA VI and XML

-click view if the user would like to visually inspect the FPGA VI

-click compile if the user would like to compile the FPGA VI from this configuration screen

by Trusted Enthusiast
on ‎04-15-2011 01:36 PM

The FPGA Wizard already does half of this (configuration based FPGA code generation).  Should we modify it to allow generic IP and XML generation?

by Active Participant griffindore
on ‎04-15-2011 03:00 PM



The FPGA Wizard is not usable for NI VeriStand. NI VeriStand requires the FPGA to be sandboxed into a very specific design pattern. See this link for more information on FPGAs in NI VeriStand: http://decibel.ni.com/content/docs/DOC-13815. Something similar to the FPGA Wizard, but specific to NI VeriStand (and in my mind completely redesigned) is required.


One requirement is to be flexible to allow generic IP, but also specify paths where generic IP can be installed so the utility automatically finds it and makes it an option. There would need to be some sort of specification for "generic IP" so that the utility would know to add it as inline to the communication loop or in a parallel loop.


Since custom components can be used in the FPGA that do not plug into the custom FPGA design pattern, I would also suggest the ability to add a custom device component to the FPGA. These components may require a DMA FIFO, so it would also need a spec file with the custom component that would allow the utility to know what to add.

by Trusted Enthusiast
on ‎04-15-2011 03:08 PM

I did not see anything in the Veristand document that could not be fairly easily implemented with the FPGA Wizard.  The FPGA Wizard has a generic core architecture which is relatively easy to customize.

by Active Participant griffindore
on ‎04-18-2011 10:54 AM

I think that would be perfect then.

by Member ekb1
on ‎04-19-2012 08:30 AM

How about just creating a wizard that will install a User provide VI and simply do all of the work necessary to expose the front panel items to Veristand?  The DMA design pattern, packing, unpacking, and XML should really never be necessary to do by a human.

by Member Ryan_S
on ‎03-25-2015 05:13 PM

I know this thread started a while back but, for anyone still looking for this functionality, a node was created on the community that gives a configuration based experience for bitpacking your I/O and automatically generates the XML for VeriStand. The FPGA XML Builder Node is available for VeriStand 2013, or higher, and can be found here.