myRIO too much device utilization & compile time

[110208004@kocaeli.edu.tr]

hello everyone

I wrote a basic program for myRIO as FPGA target. I use just a button and a led. But it takes 40 minutes to compile it and it says that it uses 44 percent of the fpga. I think it is impossible how is it possible i dont have any other code on the project.  Actually my program works correct with no problem. But it is not logical. I use sbRIO too there i have meaningfull results as device utilization

I have installed LabVİEW 2013 for myRIO, LabVIEW FPGA, LabVIEW Compile Farm 2013 and LabVIEW Xilinx Tool. Is there any other software needed ? 

Can anybody say something about this

[cade]

Hello,

Could you tell me which sbRIO you are using? Assuming your FPGA code is the same for both devices, you are most likely seeing diifferent results on each one because they use different FPGAs. The myRIO uses a Zilinx Zync FPGA which has been reported to require more FPGA usage than other FPGAs at compile time. As you have observed, this should not affect perfromance of your application.

If you are still looking to minimize the FPGA usage on your myRIO, please take a look at the following resource.

How can I Optimize/Reduce FPGA Resource Usage and/or Increase Speed?:

http://digital.ni.com/public.nsf/allkb/311C18E2D635FA338625714700664816?OpenDocument

I hope this helps!

Regards,

[T-REX$ · Accepted solution]

Duplicate Post: http://forums.ni.com/t5/LabVIEW/too-much-device-utilization-amp-compile-time/m-p/2897846

[110208004@kocaeli.edu.tr]

I think it is impossible that it uses 40 percent of the fpga. I try to make the suggestion of you before (about optimizing). it does'nt work.

T-REX$ yes duplicate post 🙂 after i don't get answers from here 🙂