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fpga project runs very slow

Hello,

 

I'm working on my first labview project on NI ELVIS. The purpose of this project is to take a photo(8 bit depth) and send it to the FPGA, where I do several operations on it's bits. I've previously learned that I should use a read-write control and send the photo piece by piece to the fpga board. I did just that, and I'm using several VI's to split the photo in 8x8 byte matrices. After that I convert each 8x1 row into a u64 number which I "feed" into the fpga(i have 8 kind of numbers in the fpga, resulting in 8x8 bytes of data). Ideally, it should work like a charm, but my biggest problem is that I'm waiting for half an hour and the vi still has'n parsed a 512x512 grayscale lenna.bmp.

 

main.png

 

That subVI contains a subVI that converts the matrices into u64 numbers and opens a VI reference to the fpga vi which does only simple logical operations. Then the data from the fpga is recomposed back into 8x8 matrices and the matrices are used to recompose the new images. In the photo there are 3 photos because I want to output the vertical edge detected image, the horizontal one and the final intersection of the two previous images. 

Could you please help me determine what is so time consuming? If needed I will upload my project. Sorry for the mess, I'm still learning how to work with labview.

 

 

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I can't really see what your VI looks like from the tiny screen shot, but if you are writing each 8x8 pieces of data to the FPGA one set at a time using the Read/Write method then it will be slow as each transaction is a separate transfer of data over the bus between the CPU and the FPGA. If you are working with an image this large, you should transfer the data using DMA FIFOs, one in each direction.

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From what I know, NI ELVIS has no support for DMA FIFOs. If I am wrong, could you post a small vi example on how to send data from and to the fpga? Also, do I have to implement something in the vhdl code to read from the fifo? My code currently xors some input std_logic_vectors and sends the output.
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Hey French91,

 

You're correct, the NI ELVIS FPGA Target (Digital Electronics FPGA Board) is a USB device, and does not support DMA. It's difficult to tell by looking at just the tiny screenshot you provided, but it looks like you may be running in Simulation on the Desktop Computer. I'm guessing this because I see a block diagram, with a running arrow and debugging options available. This would make your algorithm considerably slower, because you're running an FPGA simulation on your desktop, not in FPGA fabric. If you right-click on the "DE FPGA Board" Target in your LabVIEW project, and navigate to the Properties window, you should see a "Debugging" category. Make sure that you have the "Execute VI on FPGA Target" radio button checked.

Cheers!

TJ G
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I think that when I took the snapshot, I had the fpga running in simulation mode. It works with the same speed(or slower on the fpga target). I will upload my project if you need to take a closer look. The main VI is read_photo.vi

The others are just subvi's or vi's used for testing.

Thanks!

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