Simulate sine wave using LabVIEW FPGA with NI-myRIO and display on real-time

[mayankb]

Hi,

I am relatively new to LabVIEW FPGA. I'm trying to test (and later implement) high-speed controllers on myRIO.

At this point, I'm trying to simulate 1kHz-10kHz sine wave using Sinewave generator express VI. I also plan to display the sine wave on the real-time (RT) using FIFO. However, I've been having a little difficulty in understaing various timing parameters.

1. How do I encode sampling frequency information while generating sine wave? (The FPGA side vi only requires the signal frequency and possibly phase and does not require loop update rate)

2. How do I estimate the number of elements in a FIFO? (i.e., the relationship among loop update rate (RT), signal frequency, sampling frequency and the number of elements in FIFO)

It'd be great if one could share a very simple program (Host and Target sides) that does something similar.

Thanks,

Mayank

[diabeticdaniel]

Mayank,

The sine wave generator express VI will generate data points based on the frequency that you specify and the FPGA clock that you are using. The express VI will change the number of periods (of the sine wave) per tick of the FPGA clock that are generated based on the frequency of the sine wave you are wanting to simulate. These two numbers are linked, meaning if you change the sine wave frequency it will also change the number of periods per tick.

The easiest way to estimate the number of elements in your FIFO will be to get a benchmark on the time it takes for the loop that is writing to the FIFO to execute. You will get a new data point every time the loop iterates, assuming you are writing a single element at a time. You also have access to the number of elements in the FIFO on the RT side by using the FIFO Read Invoke Method. You can read zero elements from the FIFO and use the Number of Elements Remaining indicator to see how many elements are in the FIFO at any time.

[mayankb]

Hi,

Thank you for your email.

I tried your suggestions, however, I am still getting very poorly sampled (but right frequency) sine wave. Not sure, where is the problem.

I'm attaching my vi files for your reference. Just wondering if you can rectify the problem.

Thanks,

Mayank

[diabeticdaniel · Accepted solution]

Mayank,

I think the problem is the data type in your FIFO. Your FIFO is configured to use a data type of I16. The problem with this is the number it outputs will only ever be -1, 0, or 1. To fix this, you should pass the sine wave data as fixed point and convert it to double on the RT side. This should drastically improve your resolution.

[ZX81]

diabeticdaniel is right.  But I looked at your .vi, and it looks like that should have been accounted for in the Sine Wave Generator.  I think your conversions and divide might be creating the problem.  Try taking all that out, and send the output of Sine Wave Generator directly to the FIFO.  (The FIFO is I16; as long as your hardware is expecting I16, it looks like it should work, at maximum amplitude.)

BTW, it is usually best to avoid division in a real-time system, especially an FPGA.  I'm sure it works in this case because you're dividing by a constant, and LabView & Xilinx are smart enough to handle it.  But you can accomplish the same thing with 'to Fixed-Point' (the bits won't change, but their meaning does).  'to Fixed-Point' is always free, and may compile much faster.

I see the myRIO has DSP slices, but I still can't find a definition of what that means--I expect it means multiplies are now easy in FPGAs (they used to use up a lot of space).  Maybe they can do division easily, too...  does anyone have a link that documents them?

[mayankb]

Thank you, diabeticdaniel. It was indeed the problem.

I have got it working now. 🙂

Thanks.