Question about myRio Hardware (ADC/DAC)

[Anton.S]

Finally I placed shift register in Loop, so AI and AO can execute in parallel manner (ADC-DAC-par).

Time of 1 Loop cycle decreased to 2.5 us (actually 2.8 us I think), this is AO time, which is longer than AI.

But suddenly I got latency increase by the value similar to 1 Loop cycle!

It is very strange and dissapointing thing.

It seems like shift register was implemented as 1st register on start of Loop and 2nd register at the end of Loop.

So latency was increased by 1 Loop cycle.

Could you share your code ?

Is it possible to run AI and AO in parallel mode with only 1 layer of register's between them ?

thanks a lot!

[Anton.S]

Code snippet for last post (AI-AO_par)

In all cases I used MSP connector since it has better slew rate on AO (2 V/us instead of 0.3 V/us on MXP).

[Anton.S]

Hi!

I found help document which is very close to my problem.
http://www.ni.com/white-paper/3749/en/

Section 4. Loop Rate vs. Latency

There is an example of non-pipelined design and pipelined design.

This is citation: " In the example above the non-pipelined implementation has a loop period of 221 clock cycles (5.5 microseconds, 181 kHz). The pipelined implementation has a loop period of 172 clock cycles (4.3 microseconds, 232 kHz), However the latency of the control loop is increased by a couple of clock cycles due to the loop overhead."

But in my case latency is increased by a couple of microseconds! It looks like a bug somewhere.