If you right-click on the FPGA VI that you have built for the target, you can select that you wish to program the bitfile to the flash on the device. This will cause the VI to be loaded to the target on poweron.
As such, make sure that you have configured (in the Build Specification for more modern LVFPGA releases, or on the FPGA device properties for older versions of LVFPGA) that it is configured to run on load such that the VI on the FPGA does not need to wait to be "run"