Myrio- Issues reading from MyRio modules and FPGA simultaneously

[zappie]

 Hi

I have some issues reading values from MyRio modules and FPGA simultaneously. The error displayed is

−61202

NiFpga_Status_FpgaBusyFpgaInterfac

.

I am not sure how to rectify it(i.e. other than using diagram disable on the myrio modules) . Could somebody help me with this?

I have attached the labview files here . 

[jred101]

Hi zappie,

Thanks for posting your code separate that really helped. I was looking at your Main VI and I see that you are opening a reference to the FPGA target and then running it immediately so when you try to run the VI of your modules the FPGA is already beeing used. To understand a bit more the process on how to run the your program, do you run the Main.vi first then the FPGA.vi after?

[zappie]

hi jred101

I have included the FPGA.vi in my project and I only run the Main.vi.  The code referenced to the FPGA.vi runs fine but the other modules aren't functional. The error each of the other modules spits out is  -61202 NiFpga_Status_FpgaBusyFpgaInterface . I don't know what to do to correct it .

@jred101 wrote:

Hi zappie,

Thanks for posting your code separate that really helped. I was looking at your Main VI and I see that you are opening a reference to the FPGA target and then running it immediately so when you try to run the VI of your modules the FPGA is already beeing used. To understand a bit more the process on how to run the your program, do you run the Main.vi first then the FPGA.vi after?

---

[Jacobson-ni]

Zappie,

The myRIO I/O Express VIs work by flashing a default bitfile to the fpga and interacting with that application through it's own read/write controls or FIFOs.  This is why the Express VI is erroring out saying that there is already a reference open.

From what I understand, if you need to use your own fpga application it usually means that you will not be able to use the express VIs.  The exception to this is if you want to continuously change the firmware of your device while it is running to switch between the two bitfiles, this comes at the cost of lowering your execution speed by a lot though.

[ZX81]

I beleive that's one of those errors to ignore.  I get that (I think it's the same one) a lot.  The issue is that the FPGA bit-file was already loaded into the FPGA, either because you have it set to load automatically on power-up, or because you ran FPGA.vi manually first, so when you call the 'Run' explicitly, it's already running.  And, like most programmers that follow the development guidelines too strictly, you pass that error around, blocking anything else from working.

I recommend you test for that error code, and ignore the error if it matches.  You should (but don't have to) use some way to let the end user know what happened, if there is some other error.  And then, drop the error, and move on with no errors to the other parts of the program (one error shouldn't usually prevent other things from working).

Finally, you may need to write to 'Timing period' after the 'Run' (of course, ignoring the 'Run' error first).

I don't recommend eliminating the 'Run', because you may hit cases where the FPGA didn't automatically re-start (like some soft resets).  But expect and ignore that error.

[zigbee1]

Thank you, I happen to try myrio for the first time and I believe I got the identical issue,

so I have an fpga file that was compiled before, it is just a simple input output read write example, then in the RT vi I try to drop in the accelerometer also and that never worked. It is either the bitfile loop or the accelerometer but not both.

To correct the situation, I understand there are 2 solutions, please correct me if I am wrong,

1. modify the fpga vi to output accelerometer values also. Wait another 20 mins for compiling then use the RT vi to get control values like before.

2. get rid of fpga completely and use RT with express vi exclusively.

Now I read somewhere that it is possible to use fpga with scan IO together, but the example they used was with modular cRIO and not myRIO which is a single chip fpga/rt solution.

Was my assumption correct ?

[ZX81]

Interesting... I had missed seeing the Hybrid mode before.  I tried something similar once (on a cRIO), but when I wasn't successful right away, I assumed it wasn't possible, and moved all my I/O into the FPGA.

I'd suggest you try it with the myRIO, and see.  Odds are, if it isn't allowed, it won't allow step 8 or won't compile or deploy.  If you'd rather not invest the time waiting for compiles, moving all the I/O to the FPGA isn't a bad option, either.  I used the 'read/write control', and front panel objects on the FPGA top-level .vi.  It isn't the most effecient, but is quick & easy.

[zigbee1]

Well, myrio is different from crio in that myrio has the fpga integrated to the processor in one chip. The example that they deployed hybrid mode assumed that you used crio and this crio I assume has modular I/O pluggins so I don't think hybrid fpga compile is possible with myrio.

The bottom line is, I think, you can go with either fpga I/O or express VI I/O and not both on the same RT vi

[zappie]

Hi guys .

I apologise for the late replies. As you guys correctly pointed out the express VI's can't be used while accessing the FPGA therefore  I implemented the whole system on the FPGA and it works fine . Thank you for the insight