MyRio PWM output duty cycle not match with the set value

[William1326]

Hi, all, thanks for reading this post.

I have a project which using MyRio to control a boost converter.  In this application, the power source of the boost converter has several different power levels will change randomly, and the output of the converter should remain at a certain voltage level. so MyRio will sensor and sampling the input voltage and current as well as the output voltage to track the power variation and adjust the duty cycle of PWM (20kHz) for the IGBT. So the basic controller consists of an ADC and a signal computing module for duty cycle calculation, and a PI module to adjust the duty cycle, then a PWM generation module, all put in the MyRio FPGA target. I also put a display box to observe the duty cycle of the PWM based on a simple conversion. 

However, when I test the whole system, it seems the controller works but the PWM duty cycle showed on the oscilloscope (real duty cycle) didn't match the duty cycle calculated by the controller (showed in the display box). For example, the required D=0.5 but the duty cycle tested is 0.7. The basic principle of adjusting the duty cycle is that the PI module will compute the error between the reference signal and duty cycle based on the values which ADC have sampled, and the error will let the duty cycle increase or decrease till the error is eliminated (0).  

Right now, I have two assumptions for this problem:

(1) There have severe mistakes in the ADC sampling and signal processing, I used voltage and current transducers to sensor the signal from converter, however, the converted gains I calculated and set in MyRio are not accurate enough (the conversion gains seemed not strictly linear) so the controller will calculate a wrong duty cycle based on the wrong values calculated from those gains. In short, the duty cycle mismatch is only caused by wrong calibration and gains from the transducer and calculation, so the MyRio is running and outputs the PWM at a wrong duty cycle which itself still regard as "the correct" status. or:

(2)  The gains and signal calculations didn't affect the duty cycle so much but the PWM generation module has something wrong so the duty cycle is somehow delayed, for example, the error from PI module finally reduced to zero, however, the counter for counting the duty cycle still not stopped (the loop rates for ADC sampling and PI module are not same ). 

I'm quite confused about this mismatch of the duty cycle, could someone analyse this problem and the assumptions I made, please?  I don't have enough time to break the whole system down and test the whole program piece by piece, but I'm certain that I set the wrong converted gains in the program (the gains are not linear when changing the power source in different power levels ) and I prefer to the first assumption.  

Thanks.

[cblanchard]

Hi William1326,

There are many components of a LabVIEW program that could cause this behavior, and it likely has to do with the timing of your VI.  Are you using timed loops in your application?  If not, I would recommend looking at the solution code on page two of this forum.  The original poster had a similar issue, and altering the timing seems to have helped.

Also, I am not sure if you have seen this link, but it includes VI's written by an NI employee that can be used to measure duty cycle and period with the myRIO.

-cblanchard