Academic Hardware Products (myDAQ, myRIO)

cancel
Showing results for 
Search instead for 
Did you mean: 

MyRIO Real-Time Target Timing Error

On myrio real-time target, I created a VI with a timed loop with 1MHz clock. The dt value is given by my input. Inside the timed loop, there is basically nothing. I tried a few different dt values. When dt >= 100us (i.e. the rate is 10KHz or less), timing is correct. When dt <= 100us (i.e. the rate is greater than 10KHz), the timing will be so wrong. One case with error would be dt = 10us (rate = 100KHz), the elapsed time goes quite slower than actual time clock.

 

Here is my block diagram.

myrio_timing_error.png

 

Can someone help me debug this issue?

 

Thanks a lot.

0 Kudos
Message 1 of 3
(4,893 Views)

Hello geliang87,

 

The reason you are experiencing this behavior is due to the fact that the period you are assigning to the timed loop is close to the duration of the iteration (you can benchmark this by using the iteration duration node inside the timed loop), which makes the iteration finish after the period time finishes. This makes the next iteration start on the third period rather than the second period.

 

Regards

Jose R
0 Kudos
Message 2 of 3
(4,855 Views)

Hi Jose,

 

Got your point. Thank you.

 

My application requires a high sampling rate (up to 100KHz). I guess I should program on fpga instead of rt target.

 

Regards,

Liang

0 Kudos
Message 3 of 3
(4,848 Views)