Memory architecture - cRio 9014

[Pakatran]

Hello everyone,

I have some questions regarding the memory architecture of the cRIO 9014 (the real time controller not the FPGA part). I am wondering what kind of architecture does it use (harvard, von neumann), the size of the registers inside the controller, the size and the levels of the cache memories. 

I am acquiring data from an analogue input, I store this data into a buffer and when the software exits the while loop I write this data to a spread sheet. But I do not understand how the system manages this dynamic buffer, and where is my data stored (cache, ram) before pushing them into the spread sheet.

I checked the forum, support and developer zone but I did not find something to answer my questions. Maybe these answers are already there but I could not find them. Can anyone give some hints please?

Thank you for your time! 

[TrottM]

Hey 

This depends on how you are buffering the data. cSeries modules sometimes have a buffer on them as well an you pull data from this as and when you need it. If you are buffering the data in an array somewhere then the size is allocated at run time and stored in RAM. 

How have you coded your application? Let us have a look and we will best try and explain what is happening.

[Pakatran]

Hello,

I uploaded the vi that includes the auto indexed tunnel which temporary keeps the data (figure - question 1). (The analog input is the NI9215)

I assume that this data is temporary stored in RAM and when the program stops it will push the data to the flash memory. Is this right? 

I am also interested in the memory architecture of the cRIO, namely, who many cache levels are there available, if there is data cache and instruction cache, and which is their size.

My last question is not really related to the memory architecture but is related with the software interrupts. The "time delay" component inside a loop structure (figure - question 3) is working as timer interrupt or the controller stays there until the end of the subtractions?

Thank you!

P.S.. Sorry for the very late response, I couldn't reply earlier. 

[TrottM]

ok the first thing that I notice with your code is that it is bad practice to auto index and array from a while loop like that. There is the potential to have two infinitely large arrays being created this.

To answer your question more directly though. The data is stored in ram whilst the program executes. This is then displayed as your spectral measurement (data still in ram) and written to file (flash memory).

The processor is a powerPC 400MHz model so this would be the architecture that the cRIO works upon.

The time delay is only controlling how often the while loop iterates. Nothing else. It is not really behaving as an interupt.

Hope that helps

[Pakatran]

Thank you for the comment about the software. Do you recommend to send the data every 'n' iterations to the file? 

I found that the cRIO that I use is based on the powerPC 400 as you mentioned, but I cannot find more details about that cache memory, bus size, registers etc. Do you have any link that contains that information. I searched many times on NI's site but I cannot retrieve this data. 

[TrottM]

NI doesnt tend to disclose specifics about components used unfortunately, but you can view usage of the device through the serial port on your rio. This is explained in the manual for the device.

hope that helps

[Pakatran]

ok, I understand  . Thank you