FPGA Fundamentals (sbRIO9636)

[AEP3]

So i finished my first LabVIEW project, compiled the FPGA VI, downloaded it to my FPGA on my target device (sbRIO9636), cut out some of the analog circuitry and components was using and integrated this board into a working prototype... even though that is a huge accomplishment for myself, i still feel very noobish and have so many more questions...

Im starting this thread because im going to be asking sucha broad spectrum of questions that all relate to the topics at hand, but i figured it would be easier to keep it in one place... i dunno im still new to this whole thing =P

Original Question:

Even though my design is working, i still dont fully understand how to prevent loops from consuming too much load from the cpu or if this design is efficient...

GerdW Replied:

On the FPGA target there is no "cpu consuming too much load" problem! The only problem you have is: does the FPGA provide enough slices/fabric for your VI and does it fulfill all timing constraints…

At the time this was all gibberish to me until i did some digging around and this is what i found:

- FPGA Target: NI sbRIO-9636

- FGPA Target Specs: Spartan-6 LX45

• 6,822 slices each containing four 6-input LUTs and eight flip-flops
• 2.1Mbits of fast block RAM
• 4 clock tiles (8 DCMs & 4 PLLs)
• 6 phased-locked loops
• 58 DSP slices
• 500MHz+ clock speeds (i thought my board has a 40MHz clock?)

Other Helpful Web References:

Understanding the LabVIEW FPGA Compile System (FPGA Module)

Understanding Timing Considerations for FPGA VIs (FPGA Module)

Optimizing FPGA VIs for Speed and Size (FPGA Module)

Introduction to FPGA Hardware Concepts (FPGA Module)

FPGA Fundamentals

I guess my main question here is as follows:

Is my circuit efficient and if not how to i go about optimizing it?

As of right now this circuit is simple and small (advanced for me) but i have big plans and a lot more functions for this design... i figured it would be a good practice to stop here and analyze what is being done to fully understand if this design meets all timing constraints in order to implement those practices into the future expansion of this circuit. Also i understand that that each FPGA is composed of a finite number of predefined resources with programmable interconnects. How to i go about further understanding how much of those resources im using and/or how vast can my design get?

i know some of my questions will cause a face palm, but just hang in there with me, ima quick learner and slowly digging deeper into understanding the FPGA 😃

im linking my Timer VI so you can see what i have done so far, i can elaborate on anything if needed...

Looking forward to your feedback!

[JefeL]

I reviewed your circuit and for the most part it looks pretty good to me. There are some implicit type conversions as indicated by the little red conversion dots and those can sometimes be problematic on FPGAs. I would try to eliminate those if possible with explicit casts.

You don’t appear to be using any resource intensive operations such as division I wouldn’t expect the code to take up much space on the FPGA. As you aren’t using a Single Cycle Timed Loop the loop will execute as fast as it can but the actual loop rate will be unknown. If you were to change the loop to Single Cycle, all of the code would try to execute at 40 MHz. If the code is too complicate for the input to propagate through the logic in the allotted period, a pipelined architecture will need to be implemented. Pipelining involves breaking the logic operations into smaller chunks that operate sequentially with each iteration of the loop. There is a good explanation found in the Help here.

[AEP3]

Good Morning,

so i took some time and started to really dig into the links i posted... i guess the answer was right in front of me the whole time.

when you go to build your project it brings up the "Compilation Status" window, i never paid attention to this window and just left the computer to go smoke for the 5 mins it was going to take to compilation -_- this window actually tells you a lot...

Question 1: Does the FPGA provide enough slices/fabric for my VI?

Web References:

Understanding the LabVIEW FPGA Compile System (FPGA Module)

Reports Available from the Compilation Status Window (FPGA Module)

If im understanding what im reading, the answer is YES. Im using 4.4% of the total available slices (used:299,Total:6822)

*see img Final Device Utilization

Question 2: Does my VI fulfill all timing constraints?

Web References:

Timing Violation Analysis Window

Fixing Timing Violations (FPGA Module) 

Optimizing FPGA VIs for Speed and Size (FPGA Module)

I still don’t fully understand this yet... Im only going to say YES to this question because my compilation completed successfully. But it is because of what i read here: Understanding Timing Considerations for FPGA VIs (FPGA Module) that makes me still wonder if i meet all timing constraints. Is there a tool or some kind of method i should be practicing to prevent timing errors... or will i only be notified during the compilation if there is a timing error?

Anyways im going to assume that im understanding all of this mainly because im not getting any errors right now =P and continue on this this design... still looking for your feedback and/or any suggestions 😃

[AEP3]

Thanks Jeff for your input!

Looks like i was writing my update this morning the same time you were - you beat me to it =P

Ill look into the link you posted and get back to you, i will also take a look at those conversion dots and read up on what those are all about

[AEP3]

Getting back to you, Jeff, about the Coercion Dots...

I was able to to find topic about it here: Coercion Dots

I see where my mistakes were:

Squarewave Generator:

My generator was inputting a "I16" into a "greater than" function and i was using a "U8" as a numeric constant with a value of 0. Well i got rid of the 'greater than" all together and used a "greater than 0" - this fixes the Coercion Dot there and eliminated an extra numeric constant i didnt need all together.

Timer Configuration Circuit (Set Time/RunTime):

Because i was using "U8" for mu numeric constants in the timmer count circuit it was outputting a "U8" and comparing it with a "U16", so if flagged and Coercioned the difference... i changed everything to "U16" and it got rid of all the Coercion Dots 😃

As for your second suggestion about pipelining, i looked at your link you posted... alot of that is way over my head right now... and is something im going to have to spend some time reading up on... but i appreciate the link because like i said this design is only going to get more complicated and i want to try and understand how to implament different way to prevent future problems, or when i do run into a problem how to go about solving it, so thank you for that - im sure it might come down to having to use that approach later in design...

[JefeL]

I am glad to hear about the progress!

The coersion or data is a significant topic and konwing how it impacts data on a FPGA can be very useful. 

The other topics, such as timing constraints and device utilization, are a little more low level and will make more sense as you delve deeper into FPGA design. So far, your application is a long way from the edge of the FPGA performance envelope. You can keep an eye on the utilization metric as you add additional functionality and see how it scales with the project progress. 

[AEP3]

Right on,

i appreciate any and all helpfull tips...

the way i see it is this is my notepad made public, i can reference this at any time durring my design and who knows maybe it will help someone else too 😃

Sorry i been so quiet lately, im in the process of researching how im going to make the leap to the next step in my design...

ill mention a little bit about it here since im still digging through the haystack and havnt made any real progress...

Phase 2 of the Timer Program:

Now that i got my timmer to tick... added controls for the safty check circuit, and have it all run for a set period on time based on the operator's input i want to be able to save the run time to a file (on the sbRIO preferably for a hard copy backup) and upload to a server. Essentially it will just be the "U16" Run Time data line that i want to save to a file so i dont think it is going to be big files to save and/or transfer.

Abstract:

- Process Complete: When "Run Time" = "Set Time" & "Start/Stop" = TRUE, create NEW & SAVE "Run Time"

- Process Interupted: When "Run Time < "Set Time" & "Start/Stop" = FALSE, create NEW & SAVE "Run Time"

Ill stop right there for now... i dont want to get to complex, baby steps im thinking...

But basically once the process has completed, i want to record the time it ran for to a file that will eventually be uploaded to a server, weather i save it to a flash card on the sbRIO itself and then upload it to the server i havnt decided yet i would like to know how to go about doing both ways for future reference. but i also want to be able to know and save how much time has elapsed even if the process was interupted before it reached its targeted time.

The speed bumps im runnign into right now is can i create code within the FPGA VI to do this or do i have to create a separate Real Time VI that does the file handling and communicates with the FPGA VI? I dont know if my questions are clear enough... lol any help on this topic would be awesome, but untill then im still trucking along poking around in the dark =P

[JefeL]

All file handling will need to be performed on the RT side of the sbRIO. 

[AEP3]

Ya it was kinda of sounding that way =(

Oh well, i got some good references over the past coupleof days, enough to make a solid attempt at making this design...

NI LabVIEW for CompactRIO Developer's Guide

Getting Started with CompactRIO - Logging Data to Disk 

Ill try and keep it simple for now and post questions and or achievements as they come up

Thanks again!

[AEP3]

So i have spent a little time this morning tinkering with this tutorial...

5. LabVIEW FPGA Tutorial - Logging Data to Disk 

After building and rebuilding this this VI i finally got it to work.

There is data being generated and saved to the target device...

One of the issues i was having was that for the TDMS Open function i thought that file path was setting it to a path on my computer... but its actually saving to the Target Device

With that now understood, i was woundering if there is somewhere that tell me how much free space im working with and how big of a file can be saved on the target device?

Aslo since it is the RealTime VI doing the file handling, is there some way to start the RealTime VI by an external switch for example, cause as of right now the only way i can see to start the file handling is when i have the RealTime VI open and i click that run button...

i dont know if that question is all that clear... im going to try and implament what i learned in this turorial and apply to my design in the mean time

Looking forward to any suggestions on this