How do I create delays for several digital outputs?

[JackStaff]

I am using a DAQ PXI 6537 card to produce four digital signals each starting at a different time. In order to create this delay the appropriate number of "0's" were placed at the front of the boolean array before converting it to a digital signal. This works in creating the delay, however using this process the delay can only be discrete increments equal to 1/sample rate, and my card can only go up to 50MHz This means I can only produce delays in 20ns increments (check my math). For my application, I need to be able to control the delay down to the nano second. The delays will usually be longer than 20 ns, but shorter than 40ns. I tried using the 'to' input of the "build waveform.vi" but it didnt seem to do anything to manipulate the data. Attached is the sub vi used to create the waveform array. The sending of the data is not a problem. Thanks in adavnce for any suggestions.

JS

[Keith.Shapiro · Accepted solution]

Hi JS,

The 6537 doesn't allow sub-sample edge placement on its I/O lines.  The best you can do is (like you noticed) single sample resolution (20 ns @ 50MHz).

Have you looked at the PXIe-6545?  It's a 200MHz board, which means you'll get 5 ns placement, PLUS the data delay functionality which lets you place your samples with ~150ps resolution with respect to the output clock.

Are you needing to change the placement of a signal within the clock period each cycle?  Or is the position fixed with respect to the clock, but needs to be placed precisely?

Thanks,

Keith Shapiro

National Instruments R&D

[Ryan_M]

Jack,

The 6537 does not have configurable timing.  You have the ability to use a falling edge which would give you 10ns of edge placement at 50MHz.

The 654x,5x, and 656x all have programmable timing with sub ns resolution.  There is a single delay applied per board but each channel can independently be generated on the rising edge of the clock, the falling edge of the clock, or on the delayed version of the clock.  Additionally, the 6545 runs up to 200MHz with as low as 125ps resolution on the data delay.

[JackStaff]

Kieth,

Thanks for your advice. That is what I was afraid of though. To answer yourquestion, the position would be fixed with respect to the clock, and since all digital signals have the same rate, they remain in the same position with respect to each other. But it seems I am stuck where I am without upgrading my hardware. 

JS

[Keith.Shapiro]

That's correct - it looks like one of the 4x or 5x devices would be good for you, but they are an upgrade from the 6537.  Ryan does a pretty good job of summarizing how they work in terms of delay.

Keith Shapiro

National Instruments R&D

[ambajja]

Hello all,

I am trying to create an echo VI to run on the Speedy-33. but I have failed to create the time delay to get the signal replayed. I really need help fast

Thanks in advance 

[Dennis_Knutson]

This question has nothing to do with the original and has nothing to do with NI Digital I/O boards. Please repost in a more appropriate forum.

[muks]

Reposted here