I copied NI's FP and did my own VI soln following there methods while leaving out some of the nit-picky things like subVIs and droppin an error handler on the block diagram. (It faster to duplicate the cases in a case structure vs subVIing parts of the code when I'm in the middle of an exam and didn't include an error handler due to the simplicity of this test (only 1 block diagram needed).
I would like those to tell me who gets the fail/pass grade here on the block diagram... following the NI rules of CLD coding that is. Heck, I'll paste what they told me about the deduction of points on the CLD.... if you apply this to there soln well judge for yourself. Maybe this will help future CLD candidate... can wait for the next exam!
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""Code repeated once should be in a subVI or points off. OK, don't copy and paste code put it in a VI
use of locals or globals or propery nodes for INDICATORS value updates are points off. Controls... well alright locals globals and sometime property nodes are ok.
Unneccessary bend in wires over say ( ohh lick my finger then waving in the air) 5 times is a nono, points off.
NOT gates are points off when using the compound arithmetic operator. "Oh use the inverter thats on the compound arithmetic, your taking a performance hit...". Ah 1 less func on the block...Well I like the look of the NOT gate, its stands out.
Errors not handled.... points off. OK wire a error clust in and out your state machine and case an error with a error handler popup func, should error happen it pops up in the user face. Hmmm, did read this as a requirement in the test spec.
Don't make your Style overly complex, this is a performance hit.... "looking for the fewest functionality on the block diagram for best performance, yada yada yada. Scalable, modular, simplest, performance, speed, minimal bends, handles errors, minimal property nodes, documents all descriptions of controls and block diagram and last but not least does the functionality work.""
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