80 MHz bandwidth in 802.11 Application Framework

[cristian94]

Hello,

I am studying the performance of the 802.11 ac standard using NI USRP 2954R. For this, I need the 80 MHz bandwidth. As the white paper states, this is possible:

Note that in the FPGA bitfiles included in the Application Framework project template, 80 MHz bandwidth support is disabled, so only options 1 to 3 are applicable. To enable options 4 and 5, the bitfile must be rebuilt with the 80 MHz Boolean enabled in the supported bandwidth cluster.

I have done this, and created the cases in the VIs for the 80 MHz bandwidth. However, I can't see results, the throughput being 0, and only 1 packet start detected.

What am I missing?

Any help is greatly appreciated.

Thanks!

Cristian

[AgentAstronaut]

Hi Cristian,

It is my understanding that you also need to redesign the bit processing modules of TX and RX to work in parallel. Besides that, it seems like you got the right thing. That is a super basic version of the answer. I am working to see if I can provide a more thorough answer.

Cheers,

Michael

[cristian94]

Hi Michael,

Thank you for your time. I could not find out (yet) what modifications should I do in the bit processing modules nor in other modules since it seems that the cases are already made for the 80 MHz bandwidth. What I found out was that in the Power Measurement module, in the FIR Low Pass Filter.gcdl the case for 80 MHz was not made, but I am not sure whether this change is enough.

I find this very intriguing...any help is appreciated..

Thanks in advance!

Regards,

Cristian

[AgentAstronaut]

Hi Cristian,

I wanted to let you know that I am still working on this. It may take some time to compile the information together.

Cheers,

Michael

[AgentAstronaut]

Here is a long awaited answer.

To support the 802.11ac 80 MHz Subcarrier Format, let us summarize the required modifications into two parts.

Part 1: Enabling the 802.11ac (80 MHz) Subcarrier Format

To enable the 802.11ac 80 MHz Subcarrier Format in the FPGA, you need to do the following:

1. Enable 80 MHz as a supported Bandwidth.
   1. Go to FPGA “802.11 FPGA STA.gvi”, then go to the first loop in the FPGA, and enable the 80 MHz bandwidth as in the following:
   2. 
   3. Rebuild the Bitfile
   4. Go to 11 Host.gvi >> 802.11 Host Init.gvi >> 802.11 Open FPGA Target.gvi and make sure the Open FPGA VI.gvi is configured for your bitfile that was compiled for 80MHz.
2. Add the VHT-MCS for 80 MHz bandwidth to the Modulation and Coding Scheme (MCS) configurations.
   1. Go to the “802.11 Host.gvi” Panel and add 80 MHz (IEEE 802.11 ac) to the Subcarrier Format Ring control.
   2. Go to the “802.11 Host.gvi” diagram and find the SubVI “802.11 Subcarrier Format to Configuration.gvi”, you can find the following modulation and coding scheme (MCS) configurations:
   3. 
   4. Add a 3^rd case to the above case structure and add the VHT-MCSs table for 80 MHz, Nss = 1. Use the following table for reference.
   5. 
   6. As a reference for the 40 MHz VHT-MCSs, see below.
3. Add channel estimation parameters for 80 MHz
   1. Navigate to the 11 Host.gvi >> 802.11 Prepare Channel Estimation.gvi and add case 3, for the 80 MHz subcarrier format.
   2. Using the image below as a reference for case 3, you should replace -58 with -122 and you should replace 117 with 245.
   3. 

Part 2: Factors to consider, when using 802.11ac (80 MHz) with USRP-2953R

The 802.11 Application Framework is ready to support 80 MHz BW. However, the 802.11ac (80 MHz) format has data rates that exceed the existing FPGA clock rate (250MHz).

If we only apply the changes from Part 1, "Enabling the 802.11ac (80 MHz) Subcarrier Format" post, then you should be able to generate and receive 80 MHz BW signals with modulation coding schemes (MCS) <= 2. The clock rate of RX and TX baseband loops is 250 MHz. That means that the maximum bit rate that can be achieved theoretically is 250 Mbit/s. More practically, the clock rate of the FPGA is around 230 Mbps. For 802.11ac : 80 MHz : MCS 5 : GI 800ns, the data rate is 234 Mbps, which is above the practical limit of the FPGA. However, the biggest bottleneck is the number of bits processed per unit of time. To support the high date rates of 80 MHz bandwidth, the bit processing module of TX and RX should be redesigned to work in parallel.

To support higher MCS levels in the TX loop TX bit processing must be switched from a serial operation to parallel such that instead of producing 1 bit at a time we are producing multiple bits. (at least two bits at every clock cycle) In the image below, the highlighted chain (in red) is the one that would need to be improved to work on at least 2 samples per cycle. Complexity wise the Serializer, Scrambler, QAM mapper and Encoder are simpler to complete. The Puncturer and Interleaver could be more complex. On the receiver side the Viterbi Decoder is most likely the most complex block.

Subsequently the symbol generation also needs to be switched to support multiple bits in one clock cycle.

Note: This 80 MHz implementation has not been tested with USRP-RIO and more modification may be needed to be done to have it work.

Cheers,

Michael

[AgentAstronaut]

I should also note that the above is not an official statement of any type and may change in the future.

[cristian94]

Hi Michael,

Thank you so much for this answer! I will tell you my results as soon as I get to work again with the USRPs.

Thank you again!

Cheers,

Cristian

[sant0sh]

Can you please elaborate on compiling the lvbit file, am using 802.11 application framework 2.1 and couldn't find step 1 and 2 of your solution. I was not able to find the bandwidth selection, and can also please share how to build, I found the remaining steps in your answer in the suite

your answer will greatly help, as am struggling for awhile to get this done

[GaryN]

Are these instructions still valid? It appears that in the time since this detailed set of instructions were originally posted, the code has gone through changes and no longer has the supported bandwidths configuration item. Is this the case?

[AgentAstronaut]

I have not gotten a chance to look at what it would take in newer versions and it is not in my priority list at the moment. Since this wasn't an official document or guide I wouldn't wait on it to be updated for the newer versions. I'm sorry for the inconvenience.