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how to use XILINX IP block "CIC filter" in Labview FPGA?

Dear All, 

I am trying to build a lockin amplifier code in Labview FPGA (using NI sbRIO9637). I need to have an anti-aliasing filter before the decimation step to suppress the noise aliasing.  Previously I tried the built-in IIR filter with integer coefficients, but its magnitude frequency response was rather poor (probably due to integer coefficient roundoff in IIR Butterworth filter from FPGA maths and analysis palette). I tried to simulate the frequency response of built-in filter , and found that its roll off is very flat (even with larger number of stages) probably due to integer coefficient truncation and scaling. For this reason I wanted to try CIC filter from XILINX IP, that should not suffer from coefficient truncation. 

Please find attached the screenshot of my main data-acquisition loop. It is ran at 80kHz and the output sampling rate is supposed to be 1-2kHz.

 

However, I am not familiar with utilization of XILINX IP blocks. The NI help pages and whitepapers shed a light into it just a little bit, as they are too short and incomplete. 

 

http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpgaconcepts/xilinxip_using/

http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpgaconcepts/integrating_hdl/

https://forums.ni.com/t5/LabVIEW/Xilinx-IPCore-CIC-decimating-filter/td-p/2888774

 

1. I don't understand, how to interface the XILINX CIC compiler IP block in my case. Especially, I don't know how to wire the   AIX4 protocol data and handshaking signals.

2. Is it efficient (from occupied space point of view) to have one XILINX IP block processing two channel data? If so, how can we manage it.

3. Does this block need to be run in a single-cycle timed loop, or can it be run in an arbitrary While loop?

4. Does some output scaling need to be performed after this filter or can I just discard the least significant bits?

 

 

 

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Hi IvanRyger,

 

I found a CIC filter already made for LabVIEW FPGA http://zone.ni.com/reference/en-XX/help/371988G-01/lvdigfiltdestk/dfd_build_cic_filter/

 

Is this useful for you?

 

Regards,

PedroR

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Dear PedroR.

I will try to install the Digital Filter Design toolbox and try this block, instead.

By the way, what is the advantage of using Xilinx IP blocks (e.g. CIC compiler)?

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Ivan,

 

I think there is not much of a difference, I imagine that because the FPGA is from Xilinx, this might represent certain advantage but as it's used in a LabVIEW code, I don't think it has this advantage.

 

My recommendation is using LabVIEW FPGA functions as much as you can, outside code hasn't been optimized for using in LabVIEW environment.

 

Regards.

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